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ZVN3306A_15 Datasheet, PDF (1/3 Pages) Diodes Incorporated – N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
N-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 60 Volt VDS
* RDSon)=5Ω
ZVN3306A
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at Tamb=25°C
Pulsed Drain Current
Gate-Source Voltage
Power Dissipation at Tamb=25°C
Operating and Storage Temperature Range
SYMBOL
VDS
ID
IDM
VGS
Ptot
Tj:Tstg
D
G
S
E-Line
TO92 Compatible
VALUE
60
270
3
± 20
625
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BVDSS
60
V
ID=1mA, VGS=0V
Gate-Source Threshold
Voltage
VGS(th)
0.8
2.4
V
ID=1mA, VDS= VGS
Gate-Body Leakage
IGSS
20
Zero Gate Voltage Drain
IDSS
0.5
Current
50
On-State Drain Current(1)
ID(on)
750
Static Drain-Source On-State RDS(on)
5
Resistance (1)
nA VGS=± 20V, VDS=0V
µA VDS=60V, VGS=0
µA VDS=48V, VGS=0V, T=125°C(2)
mA VDS=18V, VGS=10V
Ω
VGS=10V,ID=500mA
Forward Transconductance(1)(2gfs
150
)
mS VDS=18V,ID=500mA
Input Capacitance (2)
Common Source Output
Capacitance (2)
Ciss
Coss
35 pF
25
pF VDS=18V, VGS=0V, f=1MHz
Reverse Transfer Capacitance Crss
(2)
8
pF
Turn-On Delay Time (2)(3)
td(on)
5
ns
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
tr
td(off)
7
ns
VDD ≈18V, ID=500mA
6
ns
Fall Time (2)(3)
tf
8
ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2%
3-375
(
2) Sample test.