DPLS4140E Datasheet, PDF (1/4 Pages) Diodes Incorporated – LOW VCE(SAT) PNP SURFACE MOUNT TRANSISTOR

DPLS4140E
LOW V_CE(SAT) PNP SURFACE MOUNT TRANSISTOR
Features
Mechanical Data
• Epitaxial Planar Die Construction
• Case: SOT-223
• Ideally Suited for Automated Assembly Processes
• Ideal for Medium Power Switching or Amplification Applications
• Lead Free By Design/RoHS Compliant (Note 1)
• "Green" Device (Note 2)
• Case Material: Molded Plastic, "Green" Molding Compound. UL
Flammability Classification Rating 94V-0
• Moisture Sensitivity: Level 1 per J-STD-020D
• Terminals: Finish - Matte Tin annealed over Copper Leadframe
(Lead Free Plating). Solderable per MIL-STD-202, Method 208
• Marking Information: See Page 4
• Ordering Information: See Page 4
• Weight: 0.115 grams (approximate)
COLLECTOR
2,4
3E
Top View
1
BASE
3
EMITTER
Device Schematic
C4
2C
1B
TOP VIEW
Pin Configuration
Maximum Ratings @T_A = 25°C unless otherwise specified
Characteristic
Collector-Base Voltage
Collector-Emitter Voltage
Emitter-Base Voltage
Continuous Collector Current
Peak Pulse Current
Symbol
V_CBO
V_CEO
V_EBO
I_C
I_CM
Value
-180
-140
-7
-4
-10
Unit
V
V
V
A
A
Thermal Characteristics
Characteristic
Power Dissipation (Note 3) @ T_A = 25°C
Thermal Resistance, Junction to Ambient Air (Note 3) @ T_A = 25°C
Operating and Storage Temperature Range
Symbol
P_D
R_θJA
T_J, T_STG
Value
1
125
-55 to +150
Unit
W
°C/W
°C
Notes:
1. No purposefully added lead.
2. Diodes Inc.'s "Green" policy can be found on our website at http://www.diodes.com/products/lead_free/index.php.
3. Device mounted on FR-4 PCB; pad layout as shown on page 4 or in Diodes Inc. suggested pad layout document AP02001, which can be found on our
website at http://www.diodes.com/datasheets/ap02001.pdf.
DPLS4140E
Document number: DS31279 Rev. 3 - 2
1 of 4
www.diodes.com
October 2008
© Diodes Incorporated