DMN66D0LW Datasheet, PDF (1/4 Pages) Diodes Incorporated – N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR

DMN66D0LW
Features
N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR
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Mechanical Data
• Low On-Resistance
• Low Gate Threshold Voltage
• Low Input Capacitance
• Fast Switching Speed
• Small Surface Mount Package
• ESD Protected Gate, 1KV (HBM)
• Lead Free/RoHS Compliant (Note 2)
• Qualified to AEC-Q101 Standards for High Reliability
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SOT-323
Case: SOT-323
Case Material: Molded Plastic. UL Flammability Classification
Rating 94V-0
Moisture Sensitivity: Level 1 per J-STD-020D
Terminals: Solderable per MIL-STD-202, Method 208
Lead Free Plating (Matte Tin Finish annealed over Alloy 42
leadframe).
Terminal Connections: See Diagram
Marking Information: See Page 3
Ordering Information: See Page 3
Weight: 0.006 grams (approximate)
Drain
D
ESD PROTECTED, 1KV
TOP VIEW
Maximum Ratings @T_A = 25°C unless otherwise specified
Characteristic
Drain-Source Voltage
Gate-Source Voltage (Note 1)
Drain Current (Note 1)
Continuous
Continuous
Continuous @ 100°C
Pulsed
Gate
Gate
Protection
Diode
Source
EQUIVALENT CIRCUIT
G
S
TOP VIEW
Symbol
V_DSS
V_GSS
I_D
Value
60
±20
115
73
800
Units
V
V
mA
Thermal Characteristics @T_A = 25°C unless otherwise specified
Characteristic
Total Power Dissipation
Thermal Resistance, Junction to Ambient
Operating and Storage Temperature Range
Symbol
P_D
R_θJA
T_J, T_STG
Value
200
625
-55 to +150
Units
mW
°C/W
°C
Electrical Characteristics @T_A = 25°C unless otherwise specified
Characteristic
OFF CHARACTERISTICS (Note 3)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Body Leakage
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Static Drain-Source On-Resistance
Forward Transconductance
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Turn-Off Delay Time
Symbol Min Typ Max Unit
Test Condition
BV_DSS 60 70
⎯
V V_GS = 0V, I_D = 10μA
@ T_C = 25°C
@ T_C = 125°C
I_DSS
⎯
⎯
1.0
500
µA V_DS = 60V, V_GS = 0V
I_GSS
⎯ ⎯ ±5 μA V_GS = ±20V, V_DS = 0V
V_GS(th) 1.2 ⎯ 2.0 V V_DS = V_GS, I_D = 250μA
@ T_J = 25°C
@ T_J = 125°C
R_{DS (ON)} ⎯
3.5
3.0
6
5
Ω ^{VGS = 5.0V, ID = 0.115A}
V_GS = 10V, I_D = 0.115A
g_FS
80 ⎯ ⎯ mS V_DS = 10V, I_D = 0.115A
C_iss
C_oss
C_rss
⎯ 23 ⎯ pF
⎯ 3.4 ⎯ pF VDS = 25V, VGS = 0V, f = 1.0MHz
⎯ 1.4 ⎯ pF
t_D(ON)
⎯ 10
⎯
ns V_DD = 30V, I_D = 0.115A, R_L = 150Ω,
t_D(OFF)
⎯
33
⎯
ns VGEN = 10V, RGEN = 25Ω
Notes:
1. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch; pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which
can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
2. No purposefully added lead.
3. Short duration pulse test used to minimize self-heating effect.
DMN66D0LW
Document number: DS31483 Rev. 1 - 2
1 of 4
www.diodes.com
July 2008
© Diodes Incorporated