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DMN66D0LDW Datasheet, PDF (1/4 Pages) Diodes Incorporated – DUAL N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR | |||
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DMN66D0LDW
DUAL N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR
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Features
Mechanical Data
⢠Dual N-Channel MOSFET
⢠Low On-Resistance
⢠Low Gate Threshold Voltage
⢠Low Input Capacitance
⢠Fast Switching Speed
⢠Small Surface Mount Package
⢠ESD Protected Gate, 1KV (HBM)
⢠Lead Free/RoHS Compliant (Note 2)
⢠Qualified to AEC-Q101 Standards for High Reliability
⢠Case: SOT-363
⢠Case Material: Molded Plastic. UL Flammability Classification
Rating 94V-0
⢠Moisture Sensitivity: Level 1 per J-STD-020C
⢠Terminals: Solderable per MIL-STD-202, Method 208
⢠Lead Free Plating (Matte Tin Finish annealed over Alloy 42
leadframe).
⢠Terminal Connections: See Diagram
⢠Marking Information: See Page 3
⢠Ordering Information: See Page 3
⢠Weight: 0.006 grams (approximate)
SOT-363
D2
G1
S1
ESD PROTECTED, 1KV
TOP VIEW
Maximum Ratings @TA = 25°C unless otherwise specified
Characteristic
Drain-Source Voltage
Gate-Source Voltage (Note 1)
Drain Current (Note 1)
Continuous
Continuous
Continuous @ 100°C
Pulsed
S2
G2
D1
TOP VIEW
Internal Schematic
Symbol
VDSS
VGSS
ID
Value
60
±20
115
73
800
Units
V
V
mA
Thermal Characteristics @TA = 25°C unless otherwise specified
Characteristic
Total Power Dissipation
Derating above TA = 25°C (Note 1)
Thermal Resistance, Junction to Ambient
Operating and Storage Temperature Range
Symbol
PD
RθJA
Tj, TSTG
Value
250
1.6
500
-55 to +150
Units
mW
mW/°C
°C/W
°C
Electrical Characteristics @TA = 25°C unless otherwise specified
Characteristic
OFF CHARACTERISTICS (Note 3)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Body Leakage
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Static Drain-Source On-Resistance
Forward Transconductance
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Turn-Off Delay Time
Symbol Min Typ Max Unit
Test Condition
BVDSS 60 70
â¯
V VGS = 0V, ID = 10μA
@ TC = 25°C
@ TC = 125°C
IDSS
â¯
â¯
1.0
500
µA VDS = 60V, VGS = 0V
IGSS
⯠⯠±5 μA VGS = ±20V, VDS = 0V
@ Tj = 25°C
@ Tj = 125°C
VGS(th) 1.2 ⯠2.0 V VDS = VGS, ID = 250μA
RDS (ON) â¯
3.5
3.0
6
5
Ω VGS = 5.0V, ID = 0.115A
VGS = 10V, ID = 0.115A
gFS
80 ⯠⯠mS VDS = 10V, ID = 0.115A
Ciss
Coss
Crss
⯠23 ⯠pF
⯠3.4 ⯠pF VDS = 25V, VGS = 0V, f = 1.0MHz
⯠1.4 ⯠pF
tD(ON)
â¯
10
â¯
ns VDD = 30V, ID = 0.115A, RL = 150Ω,
tD(OFF)
â¯
33
â¯
ns VGEN = 10V, RGEN = 25Ω
Notes:
1. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch; pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which
can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
2. No purposefully added lead.
3. Short duration pulse test used to minimize self-heating effect.
DMN66D0LDW
Document number: DS31232 Rev. 4 - 2
1 of 4
www.diodes.com
February 2008
© Diodes Incorporated
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