BSS138DW_1 Datasheet, PDF (1/5 Pages) Diodes Incorporated – DUAL N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR

SPICE MODELS: BSS138DW
BSS138DW
DUAL N-CHANNEL ENHANCEMENT
MODE FIELD EFFECT TRANSISTOR
Features
· Low On-Resistance
· Low Gate Threshold Voltage
· Low Input Capacitance
· Fast Switching Speed
· Available in Lead Free/RoHS Compliant Version (Note 4)
· Qualified to AEC-Q101 Standards for High Reliability
Mechanical Data
· Case: SOT-363
· Case Material: Molded Plastic. UL Flammability
K
Classification Rating 94V-0
A
D₂
G₁
S₁
BC
S₂
G₂
D₁
G
H
SOT-363
Dim Min Max
A
0.10 0.30
B
1.15 1.35
C
2.00 2.20
D
0.65 Nominal
M
F
0.30 0.40
H
1.80 2.20
· Moisture Sensitivity: Level 1 per J-STD-020C
J
· Terminals: Solderable per MIL-STD-202, Method 208
DF
L
· Also Available in Lead Free Plating (Matte Tin Finish
D₂
G₁
S₁
annealed over Alloy 42 leadframe). Please see Ordering
Information, Note 6, on Page 2
J
¾
0.10
K
0.90 1.00
L
0.25 0.40
M
0.10 0.25
· Terminal Connections: See Diagram
a
0°
8°
· Marking Code (See Page 2): K38
· Ordering & Date Code Information: See Page 2
S₂
G₂
D₁
All Dimensions in mm
· Weight: 0.006 grams (approximate)
Maximum Ratings ^{@ TA = 25°C unless otherwise specified}
Characteristic
Drain-Source Voltage
Drain-Gate Voltage (Note 3)
Gate-Source Voltage
Drain Current (Note 1)
Total Power Dissipation (Note 1)
Thermal Resistance, Junction to Ambient
Operating and Storage Temperature Range
Continuous
Continuous
Symbol
V_DSS
VDGR
V_GSS
I_D
P_d
R_qJA
T_j, T_STG
Electrical Characteristics ^{@ TA = 25°C unless otherwise specified}
BSS138DW
50
50
±20
200
200
625
-55 to +150
Units
V
V
V
mA
mW
°C/W
°C
Characteristic
OFF CHARACTERISTICS (Note 2)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Body Leakage
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Static Drain-Source On-Resistance
Forward Transconductance
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Turn-Off Delay Time
Symbol Min Typ Max Unit
Test Condition
BV_DSS
50
I_DSS
¾
I_GSS
¾
75
¾
V VGS = 0V, ID = 250mA
¾
0.5
µA VDS = 50V, VGS = 0V
¾ ±100 nA VGS = ±20V, VDS = 0V
V_GS(th)
0.5
1.2
1.5
V VDS = VGS, ID = 250mA
R_{DS (ON)} ¾
1.4 3.5
W VGS = 10V, ID = 0.22A
g_FS
100
¾
¾
mS VDS =25V, ID = 0.2A, f = 1.0KHz
C_iss
¾
¾
50
pF
C_oss
¾
¾
25
pF
VDS = 10V, VGS = 0V
f = 1.0MHz
C_rss
¾
¾
8.0
pF
t_D(ON)
¾
¾
20
ns _{VDD = 30V, ID = 0.2A,}
t_D(OFF)
¾
¾
20
ns ^{RGEN = 50W}
Note: 1. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch; pad layout as shown on Diodes Inc. suggested pad layout
document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.
2. Short duration test pulse used to minimize self-heating effect.
3. RGS £ 20KW.
4. No purposefully added lead.
DS30203 Rev. 8 - 2
1 of 5
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BSS138DW
ã Diodes Incorporated