Q48SG12034NRFA Datasheet, PDF (11/26 Pages) Delta Electronics, Inc. – Delphi Series Q48SG Quarter Brick Family Full Digital Control DC/DC Power Modules:

FEATURES DESCRIPTIONS (CON.)
If system has no redundancy requirement, the module
can be parallel directly for higher power without adding
external oring-fet; whereas, If the redundancy function is
required, the external oring-fet should be added.
For a normal parallel operation the following
precautions must be observed:
1. The current sharing accuracy equation is:
X% = | Io – ( Itotal / N ) | / Irated, Where,
Io is the output current of per module;
Itotal is the total load current;
N is parallel module numbers;
Irated is the rated full load current of per module.
2. To ensure a better steady current sharing accuracy,
below design guideline should be followed:
a) The inputs of the converters must be connected to the
same voltage source; and the PCB trace resistance
from Input voltage source to Vin+ and Vin- of each
converter should be equalized as much as possible.
b) The PCB trace resistance from each converter’s
output to the load should be equalized as much as
possible.
c) For accurate current sharing accuracy test, the
module should be soldered in order to avoid the
unbalance of the touch resistance between the modules
to the test board.
3. To ensure the parallel module can start up
monotonically without trigging the OCP circuit, below
design guideline should be followed:
a) Before all the parallel module finished start up, the
total load current should be lower than the rated current
of 1 module.
b) The ON/OFF pin of the converters should be
connected together to keep the parallel modules start up
at the same time.
c) The under voltage lockout point will slightly vary from
unit to unit. The dv/dt of the rising edge of the input
source voltage must be greater than 1V/ms to ensure
that the parallel module start up at the same time.
PMBus Communication
The module has a digital PMBus interface to allow the
module to be monitored, controlled and configured by
the system. The module supports 4 PMBus signal lines,
Data, Clock, SMBALERT (optional), Control (C2 pin,
optional), and 2 Address line Addr0 and Addr1. More
detail PMBus information can be found in the PMB
Power Management Protocol Specification, Part I and
part II, revision 1.2; which is shown in http://pmbus.org .
Both 100kHz and 400kHz bus speeds are supported by
the module. Connection for the PMBus interface should
be following the High Power DC specifications given in
section 3.1.3 in the SMBus specification V2.0 or the Low
Power DC specifications in section 3.1.2. The complete
SMBus specification is shown in http://smbus.org.
DS_Q48SG12034_06272013
The module supports the Packet Error Checking (PEC)
protocol. It can check the PEC byte provided by the
PMBus master, and include a PEC byte in all message
responses to the master. And the module also can
communicate with the master that does not implement
the PEC mechanism.
SMBALERT protocol is also supported by the module.
SMBALERT line is also a wired-AND signal; by which
the module can alert the PMBUS master via pulling the
SMBALERT pin to an active low. There are two ways
that the master and the module response to the alert of
SMBALERT line.
One way is for the module used in a system that does
not support Alert Response Address (ARA). The module
is to retain it’s resistor programmed address, when it is in
an ALERT active condition. The master will
communicate with the slave module using the
programmed address, and using the various
READ_STATUS commands to find who cause for the
SMBALERT. The CLEAR_FAULTS command will clear
the SMBALERT.
The other way is for the module used in a system that
does support Alert Response Address (ARA). In this case,
the master simultaneously accesses all SMBALERT
devices through the ARA. Only the device which pulled
SMBALERT low will acknowledge the ARA. The master is
expected to perform the modified received byte operation
to get the address of the alert slave, and retire the
SMBALERT active signal. And then, the alter slave will
return to it’s resistor programmed address, allowing
normal master-slave communications to proceed.
If more than one slave pulls SMBALERT line low, the
lowest address slave will win communication rights via
standard arbitration during the slave address transfer.
After acknowledging the ARA, the lowest address slave
must disengage its SMBALERT pull down. If the master
still sees SMBALERT line low, it knows to send another
ARA and ask again “Now, who is holding the alert down”.
The second slave is now locked-up and can’t responsive.
But the solution is easy; the master should now initiate a
“dummy command”, for example read command on the
bus and read any parameter from any slave. After this, the
second slave (the one that lost arbitration in the first run)
will be released. Now, if master sends the second ARA,
the second slave will provide its address to the Master.
The module contains a data flash used to store
configuration settings, which will not be programmed into
the device data flash automatically. The
STORE_DEFAULT_ALL command must be used to
commit the current settings are transfer from RAM to
data flash as device defaults.
PMBUS Addressing
The Module has flexible PMBUS addressing capability.
When connect different resistor from Addr0 and Addr1
pin to GND pin, 64 possible addresses can be acquired.
The address is in the form of octal digits; Each pin offer
one octal digit, and then combine together to form the
decimal address as shown in below.
Address = 8 * ADDR1 + ADDR0
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