Q48SD Datasheet, PDF (10/24 Pages) Delta Electronics, Inc. – Industry standard, DOSA compliant pin out

FEATURES DESCRIPTIONS (CON.)
If system has no redundancy requirement, the module
can be parallel directly for higher power without adding
external oring-fet; whereas, If the redundancy function is
required, the external oring-fet should be added.
Vin+
Module I
On/off
Vo+
Current
Sharing
Vin
Vin-
Vo-
Load
Vin+
Module II
On/off
Vo+
Current
Sharing
Vin-
Vo-
Figure 18: Parallel and active current sharing configuration for
no redundancy requirement system
In order to keep the good stability of the parallel system,
below layout guideline should be followed:
1. The trace connected the current sharing pin of
Module I and Module II should be as short as possible.
2. The layout loop from Module I current sharing pin to
Module II current sharing pin, to Module II Vo- pin, and
come back to Module I Vo- pin should be as small as
possible.
3. The dc voltage drop from Module I Vo- pin to Module
II Vo- pin should be as small as possible.
PMBus Communication
The module has a digital PMBus interface to allow the
module to be monitored, controlled and configured by
the system. The module supports 4 PMBus signal lines,
Data, Clock, SMBALERT (optional), Control (C2 pin,
optional), and 2 Address line Addr0 and Addr1. More
detail PMBus information can be found in the PMB
Power Management Protocol Specification, Part I and
part II, revision 1.2; which is shown in http://pmbus.org .
Both 100kHz and 400kHz bus speeds are supported by
the module. Connection for the PMBus interface should
be following the High Power DC specifications given in
section 3.1.3 in the SMBus specification V2.0 or the Low
Power DC specifications in section 3.1.2. The complete
SMBus specification is shown in http://smbus.org.
The module supports the Packet Error Checking (PEC)
protocol. It can check the PEC byte provided by the
PMBus master, and include a PEC byte in all message
responses to the master. And the module also can
communicate with the master that does not implement
the PEC mechanism.
SMBALERT protocol is also supported by the module.
SMBALERT line is a wired-AND signal just as the
CLOCK and DATA signals; by which the module can
alert the PMBus master that it has an active status or
alarm condition via pulling the SMBALERT pin to an
active low. There are two ways that the master and the
module response to the alert o f SMBALERT line.
One way is for the module used in a system that does
not support ARA. The factory default state for the
module is to retain it’s resistor programmed address,
when it is in an ALERT active condition, and not respond
to the ARA. The master will communicate with the slave
module using the programmed address, and using the
various READ_STATUS commands to find who cause
for the SMBALERT. The CLEAR_FAULTS command
will clear the SMBALERT.
The other way is for the module used in a system that
does support ARA. Bit 4 of the MFR_ARA_CONFIG
command can be used to reconfigure the module to
utilize Alert Response Address (ARA). In this case, the
module will no longer respond to its programmed
address. The master simultaneously accesses all
SMBALERT devices ARA; only the device which pulled
SMBALERT low will acknowledge the ARA. The master
is expected to perform the modified received byte
operation to get the address of the alert slave, and retire
the SMBALERT active signal. And then, the alter slave
will return to it’s resistor programmed address, allowing
normal master-slave communications to proceed.
If more than one device pulls SMBALERT line low, the
lowest address device will win communication rights via
standard arbitration during the slave address transfer.
After acknowledging the slave address the device must
disengage its SMBALERT pulldown. If the master still
sees SMBALERT line low when the message transfer is
complete, it knows to read the ARA again.
The module contains a data flash used to store
configuration settings, which will not be programmed
into the device data flash automatically. The
STORE_DEFAULT_ALL command must be used to
commit the current settings are transfer from RAM to
data flash as device defaults.
PMBUS Addressing
The Module has flexible PMBUS addressing capability.
When connect different resistor from Addr0 and Addr1
pin to GND pin, 64 possible addresses can be acquired.
The address is in the form of octal digits; Each pin offer
one octal digit, and then combine together to form the
decimal address as shown in below.
Address = 8 * ADDR1 + ADDR0
10
DS_Q48SD12025_05032012