D16550 Datasheet, PDF (5/7 Pages) Digital Core Design – Configurable UART with FIFO ver 2.08

DLL or DLM to prevent long counts on initial
load.
Modem Control Logic controls the interface
with the MODEM or data set (or a peripheral
device emulating a MODEM).
Interrupt Controller - D16550 consists fully
prioritized interrupt system controller. It
controls interrupt requests to the CPU and
interrupt priority. Interrupt controller contains
Interrupt Enable (IER) and Interrupt
Identification (IIR) registers.
Receiver Control - Receiving starts when the
falling edge on Serial Input (SI) during IDLE
State is detected. After starting the SI input is
sampled every 16 internal baud cycles as it is
shown in figure below. When the logic 1 state
is detected during START bit it means that the
False Start bit was detected and receiver back
to the IDLE state.
Receiver FIFO - The Rx FIFO is 16 levels
deep, it receives data until the number of
bytes in the FIFO equals the selected interrupt
trigger level. At that time if Rx interrupts are
enabled, the UART will issue an interrupt to
the CPU. The Rx FIFO will continue to store
bytes until it holds 16 of them. It will not
accept any more data when it is full. Any more
data entering the Rx shift register will set the
Overrun Error flag.
Transmitter Control module controls
transmission of written to THR (Transmitter
Holding register) character via serial output
SO. The new transmission starts on the next
overflow signal of internal baud generator,
after writing to THR register or Transmitter
FIFO. Transmission control contains THR
register and transmitter shift register.
Transmitter FIFO - the Tx portion of the
UART transmits data through SO as soon as
the CPU loads a byte into the Tx FIFO. The
UART will prevent loads to the Tx FIFO if it
currently holds 16 characters. Loading to the
Tx FIFO will again be enabled as soon as the
next character is transferred to the Tx shift
register. These capabilities account for the
largely autonomous operation of the Tx. The
UART starts the above operations typically
with a Tx interrupt.
PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
Speed
grade
Logic Cells
F_max
CYCLONE
-6
CYCLONE 2 -6
STRATIX
-5
STRATIX 2
-3
STRATIXGX -5
MERCURY
-5
452¹
461¹
452¹
388¹
452¹
513¹
153 MHz
165 MHz
189 MHz
241 MHz
184 MHz
134 MHz
EXCALIBUR -1
APEX II
-7
APEX20KC -7
APEX20KE -1
APEX20K
-1V
ACEX1K
-1
FLEX10KE
-1
479¹
480¹
479¹
479¹
479¹
500¹
500¹
131 MHz
157 MHz
141 MHz
123 MHz
94 MHz
104 MHz
102 MHz
1_{- FIFOs implemented in EAB’s – 304 Bits}
Core performance in ALTERA® devices
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