DFPMU Datasheet, PDF (3/5 Pages) Digital Core Design – Floating Point Coprocessor

SYMBOL
datai(31:0)¹
addr(4:2)²
we
datao(31:0)¹
irq
cs
rst
clk
Information about shifted-out bits are stored
for rounding process.
Control Unit – manages execution of all
instructions and internal operation required to
execute particular function.
datai(31:0)¹
datao(31:0)¹
irq
addr(4:2)²
we
cs
Interface
Mantissa
Align
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
Input Global system clock
rst
Input Global system reset
cs
datai[31:0]¹
addr[4:2]²
Input
Input
Input
Chip select for read/write
Data bus input
Register address to read/write
we
datao[31:0]¹
Input Data write enable
Output Data bus output
irq
Output Interrupt request indicator
1 – data bus can be configured as 8-, 16- or 32- bit
depends on processor’s bus size
2 – address bus is aligned to work with 8- (3:0), 16-
(3:1) or 32- (4:2) bit processors
BLOCK DIAGRAM
Mantissa – performs operations on mantissa
part of number. The addition, subtraction,
multiplication, division, square root, compari-
son and conversion operations are executed
in this module. It contains mantissas and
work registers.
CORDIC – performs trigonometric operations
on input data. The sine, cosine, tangent and
arctangent operations are executed in this
module. It contains three work registers.
Exponent – performs operations on expo-
nent part of number. The addition, subtrac-
tion, shifting, comparison and conversion
operations are executed in this module. It
contains exponents and work registers.
Align – performs the numbers analyze
against IEEE-754 standard compliance. In-
formation about the data classes are passed
as result to appropriate internal module.
Shifter – performs mantissa shifting during
normalization, denormalization operations.
Exponent
Shifter
CORDIC
clk
rst
Control
Unit
Interface – makes interface between exter-
nal device and DFPMU internal 32-bit mod-
ules. It contains data, control and status reg-
isters. It can be configured to work with 8-,
16- and 32-bit processors.
PERFORMANCE
The following table gives a survey about
the Core area and performance in the AL-
TERA® devices after Place & Route (all key
features have been included):
Device
Speed
grade
Logic Cells
F_max
APEX20KE
-1
5150
50 MHz
APEX20KC
-7
5150
58 MHz
APEX-II
-7
5150
73 MHz
CYCLONE
-6
4650
90 MHz
CYCLONE-II
-6
4520
96 MHz
STRATIX
-5
4460
108 MHz
STRATIX-II
-3
3300
168 MHz
Core performance in ALTERA® devices
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.