DFPMUL Datasheet, PDF (2/3 Pages) Digital Core Design – Floating Point Pipelined Multiplier Unit

tation. It also permits FPGA prototyping be-
fore ASIC production.
Unlimited Designs license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
● Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
SYMBOL
adatai(31:0) datao(31:0)
bdatai(31:0)
ofo
ufo
en
ifo
rst
clk
PINS DESCRIPTION
PIN
clk
rst
en
adatai[31:0]
bdatai[31:0]
datao[31:0]
ofo
ufo
ifo
TYPE
DESCRIPTION
Input Global system clock
Input Global system reset
Input Enable computing
Input A data bus input
Input B data bus input
Output Data bus output
Output Overflow flag
Output Underflow flag
Output Invalid result flag
BLOCK DIAGRAM
adatai(31:0)
bdatai(31:0)
en
rst
clk
Arguments
Checker
Main FP
Pipelined Unit
Result
Composer
datao(31:0)
ofo
ufo
ifo
Arguments Checker - performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
Main FP Pipelined Unit - performs floating
point multiply function. Gives the complex
information about the results and makes final
flags settings.
Result Composer - performs result rounding
function, data alignment to IEEE-754 stan-
dard, and the final flags setting.
PERFORMANCE
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route :
Device
Speed
grade
Logic Cells
F_max
FLEX10KE
-1
1340
40 MHz
ACEX1K
-1
1340
40 MHz
APEX20K
-1
1210
50 MHz
APEX20KE
-1
1210
50 MHz
APEX20KC
-7
1210
51 MHz
APEX-II
-7
1210
67 MHz
MERCURY
STRATIX
-5
1290
77 MHz
-5
440+8M¹ 93 MHz
CYCLONE
STRATIX-II
CYCLONE-II
-6
1170
72 MHz
-3
410+8M¹ 134 MHz
-6
480+8M¹ 117 MHz
1_{- 9-bit DSP block}
Core performance in ALTERA® devices
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.