DFPCOMP Datasheet, PDF (2/3 Pages) Digital Core Design – Floating Point Comparator Unit

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SYMBOL
adatai(31:0)
gto
bdatai(31:0)
eqo
lto
en
ifo
rst
clk
PINS DESCRIPTION
PIN
clk
rst
en
adatai[31:0]
bdatai[31:0]
gto
eqo
lto
ifo
TYPE
DESCRIPTION
Input Global system clock
Input Global system reset
Input Enable computing
Input A data bus input
Input B data bus input
output A>B output
output A=B output
output A<B output
output Invalid result flag
BLOCK DIAGRAM
adatai(31:0)
bdatai(31:0)
Arguments
Checker
Main FP
Pipelined Unit
gto
eqo
lto
ifo
en
rst
clk
Arguments Checker - performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
Main FP Pipelined Unit - performs floating
point compare function. Gives the complex
information about the results and makes final
flags settings.
PERFORMANCE
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route :
Device
Speed
grade
Logic Cells
F_max
FLEX10KE
-1
83
81 MHz
ACEX1K
-1
83
82 MHz
APEX20K
-1
79
60 MHz
APEX20KE
-1
79
76 MHz
APEX20KC
-7
79
98 MHz
APEX-II
-7
79
118 MHz
MERCURY
-5
85
178 MHz
STRATIX
-5
82
152 MHz
CYCLONE
-6
81
140 MHz
STRATIX-II
-3
66
225 MHz
CYCLONE -II
-6
81
141 MHz
Core performance in ALTERA® devices
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