D8254 Datasheet, PDF (2/4 Pages) Digital Core Design – Programmable Interval Timer

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SYMBOL
PINS DESCRIPTION
PIN TYPE
DESCRIPTION
rst
input Global reset
datai(7:0) input Processor data bus (input)
addr(1:0) input Processor address lines
cs
input Chip select
rd
input Processor read strobe
wr
input Processor write strobe
clk0
input Clock input for Counter 0
gate0
input Gate input for Counter 0
clk1
input Clock input for Counter 1
gate1
input Gate input for Counter 1
clk2
input Clock input for Counter 2
gate2
input Gate input for Counter 2
datao(7:0) output Processor data bus (output)
out0
output Output of Counter 0
out1
output Output of Counter 1
out2
output Output of Counter 2
BLOCK DIAGRAM
rst
addr(1:0)
wr
rd
cs
datai(7:0)
datao(7:0)
Read/Write
Logict
Data Bus
Buffer
Counter 0
Counter 1
clk0
gate0
out0
clk1
gate1
out1
rst
datai(7:0) datao(7:0)
Control Word
Register
Counter 2
clk1
gate1
out1
addr(1:0)
cs
rd
wr
clk0
gate0
clk1
gate1
clk2
gate2
out0
out1
out2
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Read Write Logic - The Read/Write Logic
accepts inputs from the system bus and gen-
erates control signals for the other functional
blocks of the D8254. ADDR(1:0) select one of
the three counters or the Control Word Regis-
ter to be read from/written into. A “low'' on the
RD input tells the D8254 that the CPU is
reading one of the counters. A “low'' on the
WR input tells the D8254 that the CPU is writ-
ing either a Control Word or an initial count.
Both RD and WR are qualified by CS; RD
and WR are ignored unless the 82C54 has
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