LTM9012 Datasheet, PDF (15/28 Pages) Linear Technology – Quad 14-Bit, 125Msps ADC with Integrated Drivers

LTM9012
Applications Information
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should be
treated as analog signals—do not route them next to digital
traces on the circuit board. There are two modes of opera-
tion for the encode inputs: the differential encode mode
(Figure 3), and the single-ended encode mode (Figure 4).
The differential encode mode is recommended for sinusoi-
dal, PECL, or LVDS encode inputs (Figure 5 and Figure 6).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
above V_DD (up to 3.6V), and the common mode range is
from 1.1V to 1.6V. In the differential encode mode, ENC^–
should stay at least 200mV above ground to avoid falsely
triggering the single-ended encode mode. For good jitter
performance ENC⁺ should have fast rise and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC^– is connected
to ground and ENC⁺ is driven with a square wave encode
input. ENC⁺ can be taken above V_DD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC⁺ threshold
is 0.9V. For good jitter performance ENC⁺ should have fast
rise and fall times.
LTM9012
V_DD
V_DD
15k
ENC⁺
ENC^–
30k
DIFFERENTIAL
COMPARATOR
9012 F03
Figure 3. Equivalent Encode Input Circuit
for Differential Encode Mode
1.8V TO 3.3V
0V
LTM9012
ENC⁺
ENC^–
30k
CMOS LOGIC
BUFFER
9012 F04
Figure 4. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
0.1µF _T1
50Ω
0.1µF
50Ω
ENC⁺
LTM9012
100Ω
0.1µF
ENC–
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
9012 F05
Figure 5. Sinusoidal Encode Drive
PECL OR
LVDS
CLOCK
0.1µF
ENC⁺
0.1µF
ENC^–
LTM9012
9012 F06
Figure 6. PECL or LVDS Encode Drive
9012f
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