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DP80390CPU_03 Datasheet, PDF (1/9 Pages) Digital Core Design – Pipelined High Performance 8-bit Microcontroller ver 3.10
DP80390CPU
Pipelined High Performance
8-bit Microcontroller
ver 3.10
OVERVIEW
DP80390CPU is an ultra high perform-
ance, speed optimized soft core of a single-
chip 8-bit embedded controller dedicated for
operation with fast (typically on-chip) and slow
(off-chip) memories. The core has been de-
signed with a special concern about perform-
ance to power consumption ratio. This ratio
is extended by an advanced power manage-
ment unit PMU.
DP80390CPU soft core is 100% binary-
compatible with the industry standard 80390 &
8051 8-bit microcontroller. There are two con-
figurations of DP80390CPU: Harward where
internal data and program buses are sepa-
rated, and von Neumann with common pro-
gram and external data bus. DP80390CPU has
Pipelined RISC architecture 10 times faster
compared to standard architecture and exe-
cutes 85-200 million instructions per second.
This performance can also be exploited to
great advantage in low power applications
where the core can be clocked over ten times
more slowly than the original implementation
for no performance penalty.
DP80390CPU is delivered with fully
automated testbench and complete set of
tests allowing easy package validation at each
stage of SoC design flow.
CPU FEATURES
● 100% software compatible with industry
standard 80390 & 8051
○ LARGE mode – 8051 instruction set
○ FLAT mode – 80390 instruction set
● Pipelined RISC architecture enables to
execute instructions 10 times faster com-
pared to standard 8051
● 24 times faster multiplication
● 12 times faster addition
● Up to 256 bytes of internal (on-chip) Data
Memory
● Up to 16M bytes of linear Program
Memory
○ 64 kB of internal (on-chip) Program Memory
○ 16 MB external (off-chip) Program Memory
● Up to 16M bytes of external (off-chip) Data
Memory
● User programmable Program Memory Wait
States solution for wide range of memories
speed
● User programmable External Data Memory
Wait States solution for wide range of
memories speed
● De-multiplexed Address/Data bus to allow
easy connection to memory
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