DFPADD Datasheet, PDF (1/3 Pages) Digital Core Design – Floating Point Pipelined Adder Unit

DFPADD
Floating Point Pipelined Adder Unit
ver 2.50
OVERVIEW
The DFPADD uses the pipelined mathemat-
ics algorithm to compute sum of two argu-
ments. The input numbers format is accord-
ing to IEEE-754 standard. DFPADD supports
single precision real number. Add operation
was pipelined up to 5 levels. Input data are
fed every clock cycle. The first result appears
after 5 clock periods latency and next results
are available each clock cycle. Full IEEE-
754 precision and accuracy were included.
APPLICATION
● Math coprocessors
● DSP algorithms
● Embedded arithmetic coprocessor
● Data processing & control
KEY FEATURES
● Full IEEE-754 compliance
● Single precision real format support
● Simple interface
● No programming required
● 5 levels pipeline
● Full accuracy and precision
● Results available at every clock
● Overflow, underflow and invalid operation
flags
● Fully configurable
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● Fully synthesizable, static synchronous
design with no internal tri-states
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation mac-
ros
◊ NCSim automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implemen-
http://www.DigitalCoreDesign.com
http://www.dcd.pl
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