DF6805 Datasheet, PDF (1/8 Pages) Digital Core Design – 8-bit FAST Microcontrollers Family

DF6805
8-bit FAST Microcontrollers Family
ver 1.04
OVERVIEW
Document contains brief description of
DF6805 core functionality. The DF6805 is a
advanced 8-bit MCU IP Core with highly so-
phisticated, on chip peripheral capabilities.
DF6805 soft core is binary-compatible with the
industry standard 68HC05 8-bit microcontrol-
ler and can achieve a performance 45-100
million instructions per second. There are
two configurations of DF6805: Harvard where
data and program buses are separated, and
von Neumann with common program and
data bus DF6805 has FAST architecture that
is 4.1 times faster compared to original im-
plementation. Core in standard configuration
has integrated on chip major peripheral func-
tion.
The DF6805 Microcontroller Core contains
full-duplex UART (Asynchronous serial com-
munications interface (SCI), and can also be
equipped with the Synchronous Serial Periph-
eral Interface SPI.
The main 16-bit, free-running timer system
has implemented two input capture lines and
two output-compare lines.
Self-monitoring circuitry is included on-chip to
protect against system errors. A computer
operating properly (COP) watchdog system
protects against software failures. An illegal
opcode detection circuit provides a non-
maskable interrupt if illegal opcode is de-
tected.
Two software-controlled power-saving modes,
WAIT and STOP, are available to conserve
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additional power. These modes make the
DF6805 IP Core especially attractive for
automotive and battery-driven applications.
DF6805 is fully customizable, which means
it is delivered in the exact configuration to
meet users requirements. There is no need to
pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
package validation at each stage of SoC de-
sign flow.
CPU FEATURES
● FAST architecture, 4.1 times faster than
the original implementation
● Software compatible with industry standard
68HC05
● Configurable Harvard or Von Neumann
architectures
● 64 bytes of System Function Registers
space (SFRs)
● Up to 64k bytes of Program Memory
● Up to 64k bytes of Data Memory
● De-multiplexed Address/Data Bus to allow
easy connection to memory
● Two power saving modes: STOP, WAI
● Ready pin allows Core to operate with slow
program and data memories
● Fully synthesizable, static synchronous
design with no internal tri-states
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