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D8259 Datasheet, PDF (1/4 Pages) Digital Core Design – Programmable Interrupt Controller | |||
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D8259
Programmable Interrupt Controller
ver 1.04
OVERVIEW
The D8259 is a soft Core of Programma-
ble Interrupt Controller. It is fully compatible
with the 82C59A device. The D8259 Core
manages up to 8-vectored priority interrupts
for processor. Programming it to cascade
allows for up to 64 vectored interrupts. More
than 64 vectored interrupts can be accom-
plished by programming to Poll Command
Mode.
D8259 can operate in all 82C59A modes,
and supports all 82C59A features:
â MCS-80/85 and 8088/8086 processor
modes
â Fully nested mode and special fully
nested mode
â Special mask mode
â Buffered mode
â Pool command mode
â Cascade mode with master or slave se-
lection
â Automatic end-of-interrupt mode
â Specific and non-specific end-of-interrupt
commands
â Automatic and Specific Rotation
â Edge and level triggered interrupt input
modes
â Reading of interrupt request register (IIR)
and in-service register (ISR) through data
bus.
â Writing and reading of interrupt mask reg-
ister (IMR) through data bus
KEY FEATURES
â 8 vectored priority interrupts
â Up to sixty-four vectored priority interrupts
with cascading
â Support for all 82C59A modes features
â MCS-80/85 and 8088/8086 processor
modes
â Fully nested mode and special fully nested
mode
â Special mask mode
â Buffered mode
â Pool command mode
â Cascade mode with master or slave selec-
tion
â Automatic end-of-interrupt mode
â Specific and non-specific end-of-interrupt
commands
â Automatic and Specific Rotation
â Edge and level triggered interrupt input
modes
â Reading of interrupt request register (IIR)
and in-service register (ISR) through data
bus
â Fully synthesizable, static design with no
internal tri-states
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD â Digital Core Design. All Rights Reserved.
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