DM9103 Datasheet, PDF (62/89 Pages) Davicom Semiconductor, Inc. – 10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface

Bit 3: PLE, Physical Layer Error
It is set to indicate a physical layer error
found during
the frame reception.
Bit 2: AE, Alignment Error
It is set to indicate the received frame
ends with a
non-byte boundary.
DM9103
3-port switch with PCI Interface
Bit 1: CE, CRC Error
It is set to indicate the received frame
ends with a
CRC error. Valid only when ED is set.
Bit 0: FOE, FIFO Overflow Error
This bit is valid for Ending Descriptor is set.
(ED = 1)
It is set to indicate a FIFO Overflow error
happens during the frame reception.
RDES1: Descriptor Status And Buffer Size
31 30 29 28 27 26 25 24 23 22
21 ~ 11
EOR CE
Buffer 2 Length
10 ~ 0
Buffer 1 Length
Bit 25: EOR, End of Ring
Set to indicate that the descriptor is
located on
the bottom of the descriptor list.
Bit 24: CE, Chain Enable
Set to indicate that the second address
is the
chained descriptor instead of the other
buffer.
Used as the indication of the Chain
RDES2: Buffer 1 Starting Address
Indicates the physical starting address of buffer 1.
31
Buffer Address 1
structure.
Bit 21-11: Buffer 2 Length
Indicates the size of the second buffer. It
has no meaning in chain type descriptor.
Bit 10-0: Buffer 1 Length
Indicates the size of the first buffer in
Ring type structure and single buffer in
Chain type
structure.
0
RDES3: Buffer 2 Starting Address
Indicates the physical starting address of buffer 2
under the Ring structure and that of the chained
31
Buffer Address 2
descriptor under the Chain descriptor structure.
0
(b). Transmit Descriptor Format
Each transmit descriptor has four doubleword
62
content and may be read or written by the host or
Preliminary datasheet
DM9103-DS-P02
September 26, 2007