DM9081_01 Datasheet, PDF (6/22 Pages) Davicom Semiconductor, Inc. – 10BASE-T Hub Controller

DM9081
10BASE-T Hub Controller
Functional Description
The DM9081 Integrated Multiport Controller is a
single chip implementation of an IEEE 802.3 Ethernet
repeater (Hub). The DM9081 chip provides eight
integral 10BASE-T ports plus two AUI ports,
comprising the basic repeater. The DM9081 is also
expandable, enabling the implementation of high port
count repeaters based on more than one DM9081
chip. The DM9081 chip complies with the full set of
repeater basic functions, as defined in Section 9 of
ISO 8802.3 (ANSI/IEEE 802.3C). These functions
are summarized below.
Repeater Function
When any single network port senses the start of a
packet on its receive lines, the DM9081 chip will
broadcast the received data to all other network ports.
The repeated data will also be presented on the
expansion port to provide multiple DM9081 chip
repeater applications.
Signal Regeneration
When re-transmitting a packet, the DM9081 chip
makes sure that the outgoing packet complies with
the 802.3 specification in terms of preamble
instructions, voltage amplitude and timing
characteristics. Data packets repeated by the
DM9081 chip will contain a minimum of 62 preamble
bits before the start of Frame Delimiter. Finally, signal
symmetry is restored to data packets repeated by the
DM9081 chip, removing jitter and distortion caused
by network cabling.
Collision Function
The DM9081 will detect and respond to collision
conditions as specified in IEEE 802.3. A multiple
DM9081 repeater (Hub) implementation also
complies with the 802.3 specification. Specifically, a
repeater based on one or more DM9081 chips will
handle the transmit collision and one-port-left
collision conditions correctly.
Auto Partition/Reconnection
The DM9081 monitors any TP ports or AUI ports and
partitions them once certain criteria are met. TP ports
and AUI ports will be partitioned under extended
duration or when frequent collisions occur. Each TP
port and the AUI port are partitioned separately, and
are independent of other network ports. The DM9081
chip will cause the port to partition under either of
following conditions.
1.A collision condition exists continuously for 1024-bit
times (for example, when the AUI port SQE signal
is active and the TP port is transmitting
simultaneously and receiving).
2.Whenever each of 32 consecutive attempts to
transmit to that port results in a collision.
Any partitioned port can be reconnected if a packet
longer than 512-bit times is transmitted or received
from that port without collision.
Fragment Extension
If the total packet length received by the DM9081 is
less than 96 bits, including preamble, the DM9081
chip will extend the repeated packet length to 96 bits
by appending a Jam sequence to the original
fragment.
Link Integrity Test
The integral TP ports implement the Link Test
function, as specified in the 802.3 10BASE-T
standard. The DM9081 will transmit Link Test pulses
to any TP port after that port transmitter has been
inactive for more than 8ms but less than 17 ms.
Conversely, if a TP port does not receive any data
packets or Link Test pulses for more than 65ms but
less than 132ms, that port will enter link fail state. A
port in link fail state will be disabled by the DM9081
chip (repeater transmit functions are disabled) until it
receives either four consecutive Link Test pulses or a
data packet. Note, however, that the DM9081 chip
will always transmit Link Test pulses to all TP ports
regardless of whether the port is enabled, partitioned,
or in link fail state.
6
Final
Version: DM9081-DS-F02
February 02, 2001