DM9003 Datasheet, PDF (5/65 Pages) Davicom Semiconductor, Inc. – 10/100 Mbps 2-port Ethernet Switch Controller with General Processor Interface

DM9003
2-port Switch with Processor Interface
6.46 VLAN Priority Map Registers (D0H~D1H) ................................................................................................. 32
6.47 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ........................ 32
6.48 Memory Data Read Command with Address Increment Register (F2H)................................................ 32
6.49 Memory Data Read Address Register (F4H) ............................................................................................. 32
6.50 Memory Data Read Address Register (F5H) ............................................................................................. 32
6.51 Memory Data Write Command without Address Increment Register (F6H).......................................... 32
6.52 Memory Data Write Command with Address Increment Register (F8H) ............................................... 33
6.53 Memory Data Write Address Register (FAH) ............................................................................................ 33
6.54 Memory Data Write Address Register (FBH) ............................................................................................ 33
6.55 TX Packet Length Registers (FCH~FDH) .................................................................................................. 33
6.56 Interrupt Status Register (FEH).................................................................................................................. 33
6.57 Interrupt Mask Register (FFH).................................................................................................................... 33
7. EEPROM FORMAT........................................................................................................ 34
8. PHY REGISTERS .......................................................................................................... 37
8.1 Basic Mode Control Register (BMCR) – 00H .............................................................................................. 38
8.2 Basic Mode Status Register (BMSR) – 01H ................................................................................................ 39
8.3 PHY ID Identifier Register #1 (PHYID1) – 02H............................................................................................. 40
8.4 PHY ID Identifier Register #2 (PHYID2) – 03H............................................................................................. 40
8.5 Auto-negotiation Advertisement Register (ANAR) – 04H.......................................................................... 40
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05H ............................................................. 41
Preliminary datasheet
5
DM9003-15-DS-P05
April 9, 2009