DM9106 Datasheet, PDF (32/92 Pages) Davicom Semiconductor, Inc. – 10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface

DM9106
3-port switch with PCI Interface
6.2.9 Reserved (CR8)
6.2.10 Management Access Register (CR9)
Bit
31:22
21
20
19
18
17
16
15
14
13:12
11
10
9:8
7:4
3
Name
RESERVED
LES
RLM
MDIN
MRW
MDOUT
MDCLK
RESERVED
RESERVED
RESERVED
ERS
EE_TYPE
RESERVED
RESERVED
CRDOUT
Default
0,RO
0,RO
0,RW
0,RO
0,RW
0,RW
0,RW
1,RO
0,RO
0,RO
0,RW
0,RO
011,RW
FH,RO
0,RW
Description
Reserved
Load EEPROM status
It is set to indicate the load of EEPROM is in progress.
Reload EEPROM
Set to reload the content of EEPROM.
MII Management Data_In
This is a read-only bit to indicate the MDIO input data, when bit 18 MRW is set.
MII Management Read/Write Mode Selection
This bit defines the Read/Write Mode for PHY MII management register access. 1
for read and 0 for write.
MII Management Data_Out
This bit is used to generate the output data signal for PHY MII management register
access.
MII Management Clock
This bit is used to generate the output clock signal for PHY MII management
register access.
Reserved.
Reserved.
Reserved.
EEPROM Selected
This bit is used to enable EEPROM access.
EEPROM type
0: 93C46
1: 93C56
Reserved
Reserved
Data_Out from EEPROM
This bit reflects the status of EEDI pin when the EEPROM access is enabled.
2
CRDIN
0,RW Data_In to EEPROM
This bit maps to EEDO pin when the EEPROM access is enabled.
1
CRCLK
0,RW Clock to EEPROM
This bit maps EECK pin when the EEPROM access is enabled
0
CRCS
0,RW Chip_Select to EEPROM
This bit maps to EECS pin when the EEPROM access is enabled
32
Preliminary datasheet
DM9106-DS-P01
July 9, 2009