DM9000B_12 Datasheet, PDF (16/63 Pages) Davicom Semiconductor, Inc. – Ethernet Controller With General Processor Interface

DM9000B
Ethernet Controller with General Processor Interface
6.2 Network Status Register (01H)
Bit
Name
Default
Description
Speed of internal PHY
7
SPEED
X,RO
0:100Mbps
1:10Mbps
This bit has no meaning when LINKST=0
Link status of internal PHY
6
LINKST
X,RO 1: link OK
0: link failed
Wakeup Event Status. Clears by read or write 1 (work in 8-bit mode)
5
WAKEST
P0, This bit will not be affected after software reset
RW/C1 1: Wakeup event
0: no wakeup event
4 RESERVED 0,RO Reserved
TX Packet 2 Complete Status. Clears by read or write 1
3
TX2END
PS0, Transmit completion of packet index 2
RW/C1 1: transmit completion of packet index 2
0: no packet in transmit or packet index 2 transmit in progress
TX Packet 1 Complete status. Clears by read or write 1
2
TX1END
PS0, Transmit completion of packet index 1
RW/C1 1: transmit completion of packet index 1
0: no packet in transmit or packet index 1 transmit in progress
RX FIFO Overflow status
1
RXOV
PS0,RO 1: Overflow
0: non-overflow
0 RESERVED 0,RO Reserved
6.3 TX Control Register (02H)
Bit
Name
Default
7 RESERVED 0,RO
6
TJDIS
PS0,RW
5
EXCECM PS0,RW
4 PAD_DIS2 PS0,RW
3 CRC_DIS2 PS0,RW
2 PAD_DIS1 PS0,RW
1 CRC_DIS1 PS0,RW
Description
Reserved
Transmit Jabber Timer (2048 bytes) control
1: Disabled.
0: Enable
Excessive Collision Mode Control
1: Still tries to transmit this packet
0: Aborts this packet when excessive collision counts more than 15
PAD Appends for Packet Index 2
0: Enable
1: Disable
CRC Appends for Packet Index 2
0: Enable
1: Disable
PAD Appends for Packet Index 1
0: Enable
1: Disable
CRC Appends for Packet Index 1
0: Enable
1: Disable
Final
16
Version: DM9000B-13-DS-F03
March 5, 2012