DM9621A Datasheet, PDF (15/66 Pages) Davicom Semiconductor, Inc. – USB2.0 to Fast Ethernet Controller

DM9621A
USB2.0 to Fast Ethernet Controller
4.2 Network Status Register (01H)
Bit
Name
Default
7
SPEED
PHS0, Media Speed Status
RW 1 = 10Mbps
0 = 100Mbps
Description
This bit is no meaning when LINKST=0.
This bit read only in internal PHY mode and it can be written in external
PHY mode.
This bit can also be forced by register 2EH bit 5 and 2.
6
LINKST
PHS0, Link Status
RO
1 = Link OK
0 = Link failed
This bit read only in internal PHY mode and it can be written in external
PHY mode.
This bit can also be forced by register 2EH bit 5 and 0.
5
WAKEST
P0,
Wakeup Event Status
W/C1 This bit is set when wakeup event status asserted.
This bit is cleared by write “1” or when wakeup mode disabled.
4 RESERVED PHS0, Reserved
RO
3 RESERVED PHS0, Reserved
RW/C1
2 RESERVED PHS0, Reserved
RW/C1
1
RXOV
PHS0, RX FIFO Overflow Status
RO
This bit is set when RX FIFO free space is less than 544-byte
This bit be cleared when RX FIFO free space is more than 2K.
0
RXRDY
PHS0, RX Packet Ready
RO
This bit is set when there are one or more packets in RX FIFO.
Final
Doc No: DM9621A-13-MCO-DS-F01
June 30, 2015
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