DM9008C Datasheet, PDF (11/52 Pages) Davicom Semiconductor, Inc. – Ethernet Controller With General Processor Interface

DM9008C
Ethernet Controller with General Processor Interface
Registers GPCR and GPR can program these pins
These pins are input ports at default.
5.2 EEPROM Interface
Pin No. Pin Name
19
EEDIO
20
EECK
21
EECS
5.3 Clock Interface
Pin No. Pin Name
43
X2
44
X1
Type
Description
I/O,PD ^{IO Data to EEPROM}
O,PD
O,PD
Clock to EEPROM
This pin is also used as the strap pin of the polarity of the INT pin
When this pin is pulled high, the INT pin is low active; otherwise the INT
pin is high active
Chip Select to EEPROM
This pin is also used as a strap pin to define the internal memory data bus
width. When it is pulled high, the memory access bus is 8-bit; Otherwise it
is 16-bit.
Type
O Crystal 25MHz Out
I Crystal 25MHz In
Description
5.4 LED Interface
Pin No. Pin Name
39
LED1
38
LED2
5.5 10M PHY/Fiber
Pin No. Pin Name
46
SD
48
BGGND
1
BGRES
2
RXVDD18
9
TXVDD18
3,4
RX+,RX-
Preliminary
Version: DM9008C-13-DS-P01
January 15, 2008
Type
O
O
Description
Speed LED
Its floating for the 10M mode of the internal PHY.
This pin also acts as ISA bus IO16 defined in EEPROM setting in 16-bit
mode.
Link / Active LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
This pin also acts as ISA bus IOWAIT or WAKE defined in EEPROM
setting in 16-bit mode.
Type
I
P
I/O
P
P
I/O
Description
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Band gap Ground, must be connect to AGND.
Band gap Pin
1.8V power output for TP RX
1.8V power output for TP TX
TP RX
11