3D7408 Datasheet, PDF (4/7 Pages) Data Delay Devices, Inc. – MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE

3D7408
APPLICATION NOTES (CONT’D)
pin (SI) of the succeeding device, as illustrated in
Figure 5. The total number of serial data bits in
a cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
To initiate a serial read, enable (AE) is driven
high. After a time t_EQV , bit 7 (MSB) is valid at
the serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
Pin 3, if unused, must be allowed to float if the
device is configured in the serial programming
mode.
SIGNAL IN IN
PROGRAMMABLE
DELAY LINE
OUT SIGNAL OUT
ADDRESS ENABLE AE
SERIAL INPUT SI
SHIFT CLOCK SC
MODE SELECT MD
LATCH
8-BIT INPUT
REGISTER
SO SERIAL OUTPUT
P0 P1 P2 P3 P4 P5 P6 P7
PARALLEL INPUTS
Figure1: Functional block diagram
PARALLEL
INPUTS
P0-P7
DELAY
TIME
PREVIOUS VALUE
PREVIOUS VALUE
t_PDX
NEW VALUE
t_PDV
NEW VALUE
Figure 2: Non-latched parallel mode (MD=1, AE=1)
ENABLE
(AE)
PARALLEL
INPUTS
P0-P7
DELAY
TIME
PREVIOUS VALUE
t_EDX
t_EW
t_DSE
NEW VALUE
t_DHE
t_EDV
NEW VALUE
Figure 3: Latched parallel mode (MD=1)
Doc #96003
DATA DELAY DEVICES, INC.
4
12/2/96
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