3D7215 Datasheet, PDF (3/4 Pages) Data Delay Devices, Inc. – MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7215 - LOW NOISE)

3D7215
APPLICATION NOTES (CONT’D)
pulse width. Therefore, to facilitate production
and device identification, the part number will
include a custom reference designator
identifying the intended frequency and duty cycle
of operation. The programmed delay accuracy of
the device is guaranteed, therefore, only for the
user specified input characteristics. Small input
pulse width variation about the selected pulse
width will only marginally impact the programmed
delay accuracy, if at all. Nevertheless, it is
strongly recommended that the engineering
staff at DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7215 delay line utilizes novel
and innovative compensation circuitry to
minimize the delay variations induced by
fluctuations in power supply and/or temperature.
The thermal coefficient is reduced to 200
PPM/C, which is equivalent to a variation , over
the 0C-70C operating range, of ±1% from the
room-temperature delay settings and/or 1.0ns,
whichever is greater. The power supply
coefficient is reduced, over the 4.75V-5.25V
operating range, to ±0.5% of the delay settings at
the nominal 5.0VDC power supply and/or 0.5ns,
whichever is greater. It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
V_DD
-0.3
7.0
V
Input Pin Voltage
V_IN
-0.3
V_DD+0.3
V
Input Pin Current
I_IN
-1.0
1.0
mA
25C
Storage Temperature
T_STRG
-55
150
C
Lead Temperature
T_LEAD
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL MIN
Static Supply Current*
I_DD
Input Threshold Voltage
V_TH
2.2
High Level Input Current
I_IH
Low Level Input Current
I_IL
High Level Output Current
I_OH
Low Level Output Current
I_OL
4.0
Output Rise & Fall Time
T_R & T_F
MAX
1.5
2.8
1
1
-4.0
2
UNITS
mA
V
µA
µA
mA
mA
ns
NOTES
V_IH = V_DD
V_IL = 0V
V_DD = 5.0V
V_OH = 4.0V
V_DD = 5.0V
V_OL = 0.4V
C_LD = 5 pf
*I_DD(Dynamic) = 5 * C_LD * V_DD * F
where: C_LD = Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C_LD) = 25 pf max
Doc #01015
DATA DELAY DEVICES, INC.
3
11/8/01
3 Mt. Prospect Ave. Clifton, NJ 07013