3D3608 Datasheet, PDF (3/7 Pages) Data Delay Devices, Inc. – 8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS

APPLICATION NOTES (CONT’D)
3D3608 & 3D3612
TRIGGER & RESET TIMING
Figure 2 shows the timing diagram of the device
when the reset input (RES) is not used. In this
case, the pulse is triggered by the rising edge of
the TRIG signal and ends at a time determined
by the address loaded into the device. While the
pulse is active, any additional triggers occurring
are ignored. Once the pulse has ended, and after
a short recovery time, the next trigger is
recognized. Figure 3 shows the timing for the
case where a reset is issued before the pulse
has ended. Again, there is a short recovery time
required before the next trigger can occur.
ADDRESS UPDATE
The 3D3608/3D3612 can operate in one of two
addressing modes. In the transparent mode (AE
held high), the parallel address inputs must
persist for the duration of the output pulse, in
accordance with Figure 4. In the latched mode,
the address data is stored internally, which
allows the parallel inputs to be connected to a
multi-purpose data bus. Timing for this mode is
also shown in Figure 4.
TRIGGER TRG
RESET RES
INPUT
LOGIC
ADDR ENABLE AE
DELAY
LINE
OSCILLATOR/
COUNTER
BIT-SHIFT LOGIC
8- OR 12-BIT LATCH
OUTPUT
LOGIC
OUT
OUTB
PULSE OUT
P0 P1
P7 P8 P9 ^{P10 P11}
Figure 1: Functional block diagram
TRIG
OUT
OUTB
t_TW
t_ID
t_PW
t_RTO
Figure 2: Timing Diagram (RES=0)
TRIG
RES
OUT
OUTB
t_TW
t_ID
t_RW
t_RD
t_RTR
Figure 3: Timing Diagram (with reset)
Doc #06010
DATA DELAY DEVICES, INC.
3
5/8/2006
3 Mt. Prospect Ave. Clifton, NJ 07013