3D3250 Datasheet, PDF (2/4 Pages) Data Delay Devices, Inc. – FIXED PULSE-WIDTH 10-TAP MILLISECOND TIMER (SERIES 3D3250)

3D3250
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D3250 timer waveforms are shown in
Figure 1. The device is composed of a number of
timers connected in series. Each timer produces
at its output a signal with a fixed pulse width
(equal to one period of the reference clock),
shifted in time. The timers are matched and
share the same compensation signals, which
minimize output-to-output deviations over
temperature and supply voltage variations.
INPUT TRIGGER CHARACTERISTICS
The period of the input signal (TRG) must be, at a
minimum, 200ns greater than the total time of the
particular device. This determines the highest
input frequency for guaranteed reliable device
operation. The input pulse width must also be
greater or equal to 10ns.
INPUT CLOCK CHARACTERISTICS
The input reference clock frequency determines
the device timing specifications and provides a
very stable reference to the compensation
circuitry to mitigate power supply and
temperature timing variations. The 3D3250
operates with an input reference clock that can
range from 31.25 MHz to 80 MHz. The clock
may run asynchronously with respect to the
trigger input. Table 1 tabulates total delays only at
preselected clock frequencies.
The device total time and the output-to-output
(incremental) times are multiples of the input
clock period as per the following equations:
T_I = T_CK * DashNumber
T_TOTAL = T_I * 10
For example, a 3D3250D-250, when operated
with a 40MHz (25ns period) reference clock, will
have an increment of 6.25us (25ns x 250) and a
total time of 62.5us.
CONSIDERATIONS
The device timing accuracy and stability stem
from the frequency source driving the 3D3250
delay line. Therefore, the input clock signal must
have excellent frequency accuracy through power
supply and temperature excursion. More
importantly, a frequency source with the minimum
possible short and long term jitter specifications
should be selected.
The device has two power (VDD & VDDA) and
two ground (GND & GNDA) pins. The VDD and
GND pins power the digital circuitry while the
VDDA and GNDA pins power the analog circuitry
within the device. Bypass of the power pins is
highly recommended, especially the VDDA pin.
High frequency lay-out techniques are
encouraged to be employed.
TRG
T1
T2
T3
T10
T_TW
T_INC1
T_OW
T_INC
T_INC
Figure 1: Timing Diagram
T_OTR
Doc #14017
DATA DELAY DEVICES, INC.
2
6/10/2014
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