3D7428 Datasheet, PDF (1/7 Pages) Data Delay Devices, Inc. – MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE

MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7428 – LOW NOISE)
3D7428
ddaeltaay ₃ ^
devices, inc.
FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Leading- and trailing-edge accuracy
• Programmable via serial or parallel interface
• Increment range: 0.25 through 20.0ns
• Delay tolerance: 0.5% (See Table 1)
• Supply current: 3mA typical
• Temperature stability: ±1.5% max (-40C to 85C)
• Vdd stability: ±0.5% max (4.75V to 5.25V)
PACKAGES
IN 1 16 VDD
AE 2 15 OUT
SO/P0 3 14 MD
P1 4 13 P7
P2 5 12 P6
P3 6 11 SC
P4 7 10 P5
GND 8 9 SI
3D7428-xx DIP
IN
SO
AE
GND
1 8 VDD
2 7 OUT
3 6 SC
4 5 SI
3D7428Z-xx SOIC
IN 1
AE 2
SO/P0 3
P1 4
P2 5
P3 6
P4 7
GND 8
16 VDD
15 OUT
14 MD
13 P7
12 P6
11 SC
10 P5
9 SI
3D7428S-xx SOL
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7428 device is a versatile 8-bit programmable monolithic delay
line. The input (IN) is reproduced at the output (OUT) without inversion,
shifted in time as per the user selection. Delay values, programmed
either via the serial or parallel interface, can be varied over 255 equal
steps according to the formula:
T_i,nom = T_inh + i * T_inc
where i is the programmed address, T_inc is the delay increment (equal
to the device dash number), and T_inh is the inherent (address zero)
delay. The device features both rising- and falling-edge accuracy.
IN
Signal Input
OUT Signal Output
MD Mode Select
AE Address Enable
P0-P7 Parallel Data Input
SC Serial Clock
SI
Serial Data Input
SO Serial Data Output
VDD +5 Volts
GND Ground
The all-CMOS 3D7428 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount
16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D7428-0.25
3D7428-0.5
3D7428-1
3D7428-1.5
3D7428-2
3D7428-2.5
3D7428-4
3D7428-5
3D7428-7.5
3D7428-10
3D7428-15
3D7428-20
DELAYS AND TOLERANCES
Inherent Delay
Delay
Delay (ns) Range (ns) Step (ns)
10.5 ± 2.0 63.75 ± 0.4 0.25 ± 0.12
10.5 ± 2.0 127.5 ± 0.5 0.50 ± 0.25
10.5 ± 2.0 255.0 ± 1.0 1.00 ± 0.50
10.5 ± 2.0 382.5 ± 1.5 1.50 ± 0.75
10.5 ± 2.0 510.0 ± 2.0 2.00 ± 1.00
10.5 ± 2.5 637.5 ± 2.5 2.50 ± 1.25
13.0 ± 4.0 1020 ± 3.2 4.00 ± 2.00
15.0 ± 5.0 1275 ± 4.0 5.00 ± 2.50
20.0 ± 7.5 1912.5 ± 6.0 7.50 ± 3.75
23.5 ± 10 2550 ± 8.0 10.0 ± 5.00
33.0 ± 15 3825 ± 12 15.0 ± 9.00
42.0 ± 20 5100 ± 16 20.0 ± 12.0
Rec’d Max
Frequency
6.25 MHz
3.12 MHz
1.56 MHz
1.04 MHz
781 KHz
625 KHz
390 KHz
312 KHz
208 KHz
156 KHz
104 KHz
78 KHz
INPUT RESTRICTIONS
Absolute Max Rec’d Min
Frequency
Pulse Width
77 MHz
80.0 ns
45 MHz
160.0 ns
22 MHz
320.0 ns
15 MHz
480.0 ns
11 MHz
640.0 ns
9.0 MHz
800.0 ns
5.6 MHz
1280.0 ns
4.5 MHz
1600.0 ns
3.0 MHz
2400.0 ns
2.2 MHz
3200.0 ns
1.5 MHz
4800.0 ns
1.1 MHz
6400.0 ns
Absolute Min
Pulse Width
6.5 ns
11.0 ns
22.0 ns
33.0 ns
44.0 ns
55.0 ns
88.0 ns
110.0 ns
165.0 ns
220.0 ns
330.0 ns
440.0 ns
NOTES: Any delay increment between 0.25 and 20 ns not shown is also available as standard.
See application notes section for more details
2004 Data Delay Devices
Doc #03003
DATA DELAY DEVICES, INC.
1
11/1/04
3 Mt. Prospect Ave. Clifton, NJ 07013