DS1307 Datasheet, PDF (9/11 Pages) Dallas Semiconductor – 64 X 8 Serial Real Time Clock

DS1307
AC ELECTRICAL CHARACTERISTICS
PARAMETER
(0°C to 70°C or -40°C to +85°C; V_CC =4.5V to 5.5V)
SYMBOL MIN TYP MAX UNITS NOTES
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
f_SCL
0
t_BUF
4.7
100
kHz
µs
Hold Time (Repeated) START Condition t_HD:STA
4.0
µs
5
LOW Period of SCL Clock
t_LOW
4.7
µs
HIGH Period of SCL Clock
t_HIGH
4.0
µs
Set-up Time for a Repeated START
t_SU:STA
4.7
µs
Condition
Data Hold Time
t_HD:DAT
0
Data Set-up Time
t_SU:DAT
250
Rise Time of Both SDA and SCL Signals
t_R
Fall Time of Both SDA and SCL Signals
t_F
Set-up Time for STOP Condition
t_SU:STO
4.7
µs
6, 7
ns
1000
ns
300
ns
µs
Capacitive Load for each Bus Line
C_B
I/O Capacitance
C_I/O
Crystal Specified Load Capacitance
400
pF
8
10
pF
12.5
pF
NOTES:
1. All voltages are referenced to ground.
2. Logic zero voltages are specified at a sink current of 5 mA at V_CC=4.5V, V_OL=GND for capacitive
loads.
3. I_CCS specified with V_CC=5.0V and SDA, SCL=5.0V.
4. V_CC=0V, V_BAT=3V.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V_IHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum t_HD:DAT has only to be met if the device does not stretch the LOW period (t_LOW) of the
SCL signal.
8. C_B - total capacitance of one bus line in pF.
9. I_CCA - SCL clocking at max frequency = 100 kHz.
10. SCL only.
11. SDA and SQW/OUT
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