DS28E04-100 Datasheet, PDF (8/36 Pages) Dallas Semiconductor – 4096-Bit Addressable 1-Wire EEPROM with PIO

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 5. Memory Map
Address locations 0000h to 021Fh are nonvolatile. Address locations 0220h to 0225 are volatile.
ADDRESS RANGE
0000h to 001Fh
0020h to 003Fh
0040h to 005Fh
0060h to 007Fh
0080h to 009Fh
00A0h to 00BFh
00C0h to 0DFh
00E0h to 00FFh
0100h to 011Fh
0120h to 013Fh
0140h to 015Fh
0160h to 017Fh
0180h to 019Fh
01A0h to 01BFh
01C0h to 01DFh
01E0h to 01FFh
0200h¹⁾ to 020Fh¹⁾
0210h¹⁾
0211h
0212h to 021Dh
021Eh to 021Fh
TYPE
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
DESCRIPTION
Data Memory Page 0
Data Memory Page 1
Data Memory Page 2
Data Memory Page 3
Data Memory Page 4
Data Memory Page 5
Data Memory Page 6
Data Memory Page 7
Data Memory Page 8
Data Memory Page 9
Data Memory Page 10
Data Memory Page 11
Data Memory Page 12
Data Memory Page 13
Data Memory Page 14
Data Memory Page 15
R/(W)
Protection Control Pages 0
to 15
R/(W)
R
N/A
R
Register Page Lock
Factory Byte
Reserved
Factory Bytes
PROTECTION CODES (NOTES)
(Protection controlled by address 0200h)
(Protection controlled by address 0201h)
(Protection controlled by address 0202h)
(Protection controlled by address 0203h)
(Protection controlled by address 0204h)
(Protection controlled by address 0205h)
(Protection controlled by address 0206h)
(Protection controlled by address 0207h)
(Protection controlled by address 0208h)
(Protection controlled by address 0209h)
(Protection controlled by address 020Ah)
(Protection controlled by address 020Bh)
(Protection controlled by address 020Ch)
(Protection controlled by address 020Dh)
(Protection controlled by address 020Eh)
(Protection controlled by address 020Fh)
55h: Write Protected; AAh: EPROM mode.
Address 0200h is associated with memory
page 0, address 0201h with page 1, etc.
(See text)
(Reads 55h or AAh)
(Undefined value)
220h
R PIO Logic State
(The lower two bits are valid)
221h
R PIO Output Latch State
(The lower two bits are valid)
222h
223h
224h
225h
R
R/W²⁾
R/W²⁾
R/W²⁾
PIO Activity Latch State
Conditional Search PIO
Selection Mask
Conditional Search Polarity
Selection
Conditional Search Control
and Status Register
(The lower two bits are valid)
1) _{Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but will neither}
write-protect the address nor activate any function.
2) _{Limited write access through Write Register command}
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