DS2153Q Datasheet, PDF (7/52 Pages) Dallas Semiconductor – E1 Single-Chip Transceiver

DS2153Q
PIN SYMBOL TYPE
DESCRIPTION
33 TCHBLK
O Transmit Channel Block. A user-programmable output that can be
forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in
applications where not all E1 channels are used, such as Fractional
E1, 384 kbps service (H0), 1920 kbps (H12), or ISDN-PRI. Also
useful for locating individual channels in drop-and-insert
applications. See Section 13 for timing details.
34
TLCLK
O Transmit Link Clock. 4 kHz to 20 kHz demand clock for the
TLINK input; controlled by TCR2. See Section 13 for timing
details.
35
TLINK
I Transmit Link Data. If enabled, this pin will be sampled on the
falling edge of TCLK to insert the Sa bits See Section 13 for timing
details.
36
TSYNC
I/O Transmit Sync. A pulse at this pin will establish either frame or
multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q
can be programmed to output either a frame or multiframe pulse at
this pin. See Section 13 for timing details.
37
DVDD
- Digital Positive Supply. 5.0 volts. Should be tied to RVDD and
TVDD pins.
38
TCLK
I Transmit Clock. 2.048 MHz primary clock. Needed for proper
operation of the parallel control port.
39
TSER
I Transmit Serial Data. Transmit NRZ serial data, sampled on the
falling edge of TCLK.
40 TCHCLK
O Transmit Channel Clock. 256 kHz clock which pulses high during
the LSB of each channel. Useful for parallel to serial conversion of
channel data. See Section 13 for timing details.
41
AD0
I/O Address/Data Bus. A 8-bit multiplexed address/data bus.
42
AD1
43
AD2
44
AD3
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