DS2760 Datasheet, PDF (6/25 Pages) Dallas Semiconductor – High Precision Li-Ion Battery Monitor

DS2760
POWER MODES
The DS2760 has two power modes: Active and Sleep. While in Active Mode, the DS2760 continually
measures current, voltage and temperature to provide data to the host system and to support current
accumulation and Li-ion safety monitoring. In Sleep Mode, the DS2760 ceases these activities. The
DS2760 enters Sleep Mode when either of the following conditions occurs:
• the PMOD bit in the Status Register has been set to 1 and the DQ line is low for
longer than 2 seconds (pack disconnection)
• the voltage on VIN drops below undervoltage threshold V_UV for t_UVD (cell depletion)
• the pack is disabled through the issuance of a SWAP command (SWEN bit =1)
The DS2760 returns to Active Mode when any of the following occurs:
• the PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled
high (pack connection)
• the PS pin is pulled low (power switch)
• the voltage on PLS becomes greater than the voltage on VIN (charger connection) with the
SWEN bit set to 0
• the pack is enabled through the issuance of a SWAP command (SWEN bit =1)
The DS2760 defaults to Active Mode when power is first applied.
LI-ION PROTECTION CIRCUITRY
During Active Mode, the DS2760 constantly monitors cell voltage and current to protect the battery from
overcharge (overvoltage), overdischarge (undervoltage) and excessive charge and discharge currents
(overcurrent, short circuit). Conditions and DS2760 responses are described in the sections below and
summarized in Table 2 and Figure 3.
LI-ION PROTECTION CONDITIONS AND DS2760 RESPONSES – Table 2
Condition
Activation
Release
Name
Threshold Delay
Response
Threshold
Overvoltage
V_IN > V_OV
t_OVD
CC high
V_IN < V_CE
Undervoltage
Overcurrent, Charge
Overcurrent, Discharge
Short Circuit
V_IN < V_UV
V_IS > V_OC(1)
V_IS < -V_OC(1)
V_SNS > V_SC
t_UVD
t_OCD
t_OCD
t_SCD
CC , DC high,
Sleep Mode
CC , DC high
DC high
DC high
V_PLS > VDD
(charger connected)
V_PLS < VDD - V_TP(2)
V_PLS > VDD - V_TP(3)
V_PLS > VDD - V_TP(3)
V_IS = V_IS1 – V_IS2. Logic high = V_PLS for CC and VDD for DC _. All voltages are with respect to VSS. I_SNS
references current delivered from pin SNS.
(1) for the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of
current: I_SNS > I_OC for charge direction and I_SNS < -I_OC for discharge direction
(2) with test current I_TST current flowing from PLS to VSS (pull-down on PLS)
(3) with test current I_TST current flowing from VDD to PLS (pull-up on PLS)
Overvoltage. If the voltage of the cell exceeds overvoltage threshold V_OV for a period longer than
overvoltage delay t_OVD, the DS2760 shuts off the external charge FET and sets the OV flag in the
Protection Register. When the cell voltage falls below charge enable threshold V_CE, the DS2760 turns the
charge FET back on (unless another protection condition prevents it). Discharging remains enabled
during overvoltage.
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