DS1620 Datasheet, PDF (6/13 Pages) Dallas Semiconductor – Digital Thermometer and Thermostat

DS1620
operation of the CLK/ CONV pin is as a normal clock in concert with DQ and RST . This bit is stored in
nonvolatile E² memory, capable of at least 50,000 writes. The DS1620 is shipped with CPU=0.
1SHOT = One–Shot Mode. If 1SHOT is 1, the DS1620 will perform one temperature conversion upon
reception of the Start Convert T protocol. If 1SHOT is 0, the DS1620 will continuously perform
temperature conversion. This bit is stored in nonvolatile E² memory, capable of at least 50,000 writes.
The DS1620 is shipped with 1SHOT=0.
For typical thermostat operation, the DS1620 will operate in continuous mode. However, for applications
where only one reading is needed at certain times or to conserve power, the one–shot mode may be used.
Note that the thermostat outputs (T_HIGH, T_LOW, T_COM) will remain in the state they were in after the last
valid temperature conversion cycle when operating in one–shot mode.
OPERATION IN STAND–ALONE MODE
In applications where the DS1620 is used as a simple thermostat, no CPU is required. Since the
temperature limits are nonvolatile, the DS1620 can be programmed prior to insertion in the system. In
order to facilitate operation without a CPU, the CLK/ CONV pin (pin 2) can be used to initiate
conversions. Note that the CPU bit must be set to 0 in the configuration register to use this mode of
operation. Whether CPU=0 or 1, the 3–wire port is active. Setting CPU=1 disables the stand–alone mode.
To use the CLK/ CONV pin to initiate conversions, RST must be low and CLK/ CONV must be high. If
CLK/ CONV is driven low and then brought high in less than 10 ms, one temperature conversion will be
performed and then the DS1620 will return to an idle state. If CLK/ CONV is driven low and remains low,
continuous conversions will take place until CLK/ CONV is brought high again. With the CPU bit set to 0,
the CLK/ CONV will override the 1SHOT bit if it is equal to 1. This means that even if the part is set for
one–shot mode, driving CLK/ CONV low will initiate conversions.
3–WIRE COMMUNICATIONS
The 3–wire bus is comprised of three signals. These are the RST (reset) signal, the CLK (clock) signal,
and the DQ (data) signal. All data transfers are initiated by driving the RST input high. Driving the RST
input low terminates communication. (See Figures 4 and 5.) A clock cycle is a sequence of a falling edge
followed by a rising edge. For data inputs, the data must be valid during the rising edge of a clock cycle.
Data bits are output on the falling edge of the clock and remain valid through the rising edge.
When reading data from the DS1620, the DQ pin goes to a high-impedance state while the clock is high.
Taking RST low will terminate any communication and cause the DQ pin to go to a high-impedance
state.
Data over the 3–wire interface is communicated LSB first. The command set for the 3–wire interface as
shown in Table 3 is as follows.
Read Temperature [AAh]
This command reads the contents of the register which contains the last temperature conversion result.
The next nine clock cycles will output the contents of this register.
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