DS1236A Datasheet, PDF (6/20 Pages) Dallas Semiconductor – MicroManager Chip

DS1236A
If the IN pin is connected to V_CCO, the NMI output will pulse low as V_CC decays to V_CCTP in the NMOS
mode (RC=0). In the CMOS mode (RC=V_CCO) the power-down of V_CC out of tolerance at V_CCTP will not
produce a pulse on the NMI pin. Given that any NMI pulse has been completed by the time V_CC decays
to V_CCTP, the NMI pin will remain high. The NMI voltage will follow V_CC down until V_CC decays to
V_BAT. Once V_CC decays to V_BAT, the NMI pin will either remain at V_OHL or enter tri-state mode as
determined by the RC pin (see “Reset Control” section).
MEMORY BACKUP
The DS1236A provides all of the necessary functions required to battery back a static RAM. First, a
switch is provided to direct SRAM power from the incoming 5-volt supply (V_CC) or from an external
battery (V_BAT), whichever is greater. This switched supply (V_CCO) can also be used to battery back a
CMOS microprocessor. For more information about nonvolatile processor applications, review the “Reset
Control” and “Wake Control” sections. Second, the same power-fail detection described in the power
monitor section is used to hold the chip enable output ( CEO ) to within 0.3 volts of V_CC or to within 0.7
volts of V_BAT. This write protection mechanism occurs as V_CC falls below V_CCTP as specified. If CEI is
low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high or
the period t_CE expires. This delay of write protection until the current memory cycle is completed prevents
the corruption of data. If CEO is in an inactive state at the time of V_CC-fail detection, CEO will be
unconditionally disabled within t_CF. During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. NO TAG shows a typical nonvolatile SRAM application. The
DS1236A unlike the DS1236 can be operated without a battery. In this method of operation the V_BAT, pin
1, must be grounded. In general, it would also be expected to have the RC, pin 8, grounded (NMOS
mode) since no battery backup is available.
FRESHNESS SEAL
In order to conserve battery capacity during initial construction of an end system, the DS1236A provides
a freshness seal that electrically disconnects the battery. This means that upon battery attach, the V_CCO
output will remain inactive until V_CC is applied. This prevents V_CCO from powering other devices when
the battery is first attached, and V_CC is not present. Once V_CC is applied, the freshness seal is broken and
cannot be invoked again without subsequent removal and reattachment of the battery.
POWER SWITCHING
When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236A may not be large enough to support the required load through
V_CCO with a reasonable voltage drop. For these applications, the PF and PF outputs are provided to gate
external power switching devices. As shown in Figure 8, power to the load is switched from V_CC to
battery on power-down, and from battery to V_CC on power-up. The DS1336 is designed to use the PF
output to switch between V_BAT and V_CC It provides better leakage and switchover performance than
currently available discrete components. The transition threshold for PF and PF is set to the external
battery voltage V_BAT, allowing a smooth transition between sources. The load applied to the PF pin from
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236A supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST, RST , and NMI outputs for volatile
processor operation versus nonvolatile battery backup or battery-operated processor applications.
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