DS5000FP_05 Datasheet, PDF (5/22 Pages) Dallas Semiconductor – Soft Microprocessor Chip

DS5000FP
PIN DESCRIPTION (continued)
PIN
NAME
FUNCTION
11, 9, 7, 5, 1,
79, 77, 75
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1.
P0.0–P0.7 It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data
bus. When used in this mode, it does not require pullups.
13, 14
16, 8, 18, 80,
76, 4, 6, 20, 24,
26, 28, 30, 33,
35, 37
V_CC
BA14–
BA0
Power Supply, +5V
Byte-Wide Address Bus Bits 14–0. This 15-bit bus is combined with the
nonmultiplexed data bus (BD7–BD0) to access NV SRAM. Decoding is
performed on CE1 and CE2 . Read/write access is controlled by R/W. BA14–BA0
connect directly to an 8k or 32k SRAM. If an 8k RAM is used, BA13 and BA14
are unconnected. Note: BA13 and BA14 are inverted from the true logical address.
BA14 is lithium backed.
71, 69, 67, 65,
61, 59, 57, 55
BD7–BD0
Byte-Wide Data Bus Bits 7–0. This 8-bit bidirectional bus is combined with the
nonmultiplexed address bus (BA14–BA0) to access NV SRAM. Decoding is
performed on CE1 and CE2 . Read/write access is controlled by R/W. BD7–BD0
connect directly to an 8k or 32k SRAM, and optionally to a real-time clock.
Read/Write (Active Low). This signal provides the write enable to the SRAMs
10
R/W on the byte-wide bus. It is controlled by the memory map and partition. The
blocks selected as Program (ROM) is write protected.
Active-Low Chip Enable 1. This is the primary decoded chip enable for memory
access on the byte-wide bus. It connects to the chip enable input of one SRAM.
74
CE1
CE1 is lithium backed. It will remain in a logic high inactive state when V_CC falls
below V_LI.
Active-Low Chip Enable 2. This chip enable is provided to bank switch to a
second block of 32k bytes of nonvolatile data memory. It connects to the chip
78
CE2 ^{enable input of one SRAM or one lithium-backed peripheral such a real-time}
clock. CE2 is lithium backed. It will remain in a logic high inactive state when
V_CC falls below V_LI.
V_CC Output. This is switched between V_CC and V_LI by internal circuits based on
the level of V_CC. When power is above the lithium input, power will be drawn
12
V_CCO from V_CC. The lithium cell remains isolated from a load. When V_CC is below V_LI,
the V_CCO switches to the V_LI source. V_CCO is connected to the V_CC pin of an
SRAM.
54
V_LI
Lithium Voltage Input. Connect to a lithium cell greater than V_LImin and no
greater than V_LImax as shown in the electrical specifications. Nominal value is +3V.
2, 3, 22, 23, 32,
42, 43, 62, 63,
72
N.C.
No Connection. Do not connect.
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