DS1087L Datasheet, PDF (5/12 Pages) Dallas Semiconductor – 3.3V Spread-Spectrum EconOscillator

3.3V Spread-Spectrum EconOscillator
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
All voltages are referenced to ground.
This is the absolute accuracy of the master oscillator frequency at the default settings.
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
T_A = +25°C.
This is the percentage frequency change from the +25°C frequency due to temperature at V_CC = 3.3V.
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.
This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. t_stab is equivalent to approximately 512 master clock cycles and depends
on the programmed master oscillator frequency.
Output voltage swings may be impaired at high frequencies combined with high output loading.
A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT > 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t_{R MAX} + t_SU:DAT = 1000ns +
250ns = 1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V_{IH MIN} of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
The maximum t_HD:DAT need only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.
C_B—total capacitance of one bus line, timing referenced to 0.9 x V_CC and 0.1 x V_CC.
Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr
max V_CC biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, and 168hr 121°C/2 ATM Steam/Unbiased
Autoclave.
(V_CC = 3.3V, T_A = +25°C, unless otherwise noted.)
Typical Operating Characteristics
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
7.5
V_CC = 3.3V
FREQUENCY = 66.6MHz
7.0 _{OE = PDN = VCC}
6.5
15pF LOAD
6.0
8.2pF LOAD
5.5
4.7pF LOAD
UNLOADED
5.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
ACTIVE SUPPLY CURRENT
vs. VOLTAGE
8.0
FREQUENCY = 66.6MHz
7.0 _{OUTPUT UNLOADED}
6.0 ^{OE = PDN = VCC}
5.0
4.0
3.0
2.0
1.0
0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VOLTAGE (V)
SUPPLY CURRENT vs. PRESCALER
7
OUTPUT UNLOADED
6
5
4
3
3.6V
2
3.3V
2.7V
1
0
1
10
100
1000
PRESCALER (DECIMAL)
_____________________________________________________________________ 5