DS1045 Datasheet, PDF (5/6 Pages) Dallas Semiconductor – 4-Bit Dual Programmable Delay Line

TEST CONDITIONS
T_A=25°C ±=3°C
V_CC= 5.0V ±=0.1V
Input Pulse = 3.0V high to 0.0V low ±=0.1V
Input Source Impedance = 50Ω maximum
Rise and fall times = 3.0 ns max. between 0.6V and 2.4V
Pulse Width = 250 ns
Period = 500 ns
Output Load = 74F04
Measurement Point = 1.5V on inputs and outputs
Output Load Capacitance = 15 pF
DS1045
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE, EA , EB = V_IH
TIMING DIAGRAM: LATCHED PARALLEL MODE
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