DS28DG02 Datasheet, PDF (4/33 Pages) Dallas Semiconductor – 2kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog

DS28DG02: 2kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
PARAMETER
SYMBOL
CONDITIONS
BATTERY MONITOR (See Figure 8)
V_BAT Trip Point
V_BTP
Measured with V_BAT
falling; trip point is user
programmable
V_BAT Monitor Trip-Point
Tolerance
Battery Test Load Current
Battery Test Duration
V_TRIPTOL
I_LOAD
t_BTPW
+25°C
-40°C to +85°C
Load applied to battery
(Notes 5, 16)
SPI INTERFACE TIMING (See Figures 9, 10)
CSZ Setup Time
CSZ Hold Time
CSZ Standby Pulse Width
(Note 5)
CSZ to High-Z at SO
SCK Clock Frequency
Data Setup Time
Data Hold Time
SCK Rise Time
SCK Fall Time
Output Valid time
t_CSS
t_CSH
t_CPH
t_CHZ
f_CLK
t_DS
t_DH
t_SCKR
t_SCKF
t_V
(Note 5)
(Note 5)
Normal communication
(Note 17)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
(Note 5)
MIN TYP MAX UNITS
2.25 2.31
2.03 2.08
1.80 1.85
1.58 1.62
-1.5
-2.5
7.5
2
2.38
2.14
1.90
1.66
+1.5
+2.5
20
V
%V_BTP
µA
s
0.4
µs
0.4
µs
0.25
2.0
µs
0.25
µs
2
MHz
50
ns
50
ns
1
µs
1
µs
0
120
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
If no battery is used, connect the V_BAT pin to V_CC. The RTC is powered by V_BAT if V_CC falls below V_CCmin.
To the first order, this current is independent of the supply voltage value.
Nominal values: 3.3V -5%, set at factory. Measured with V_CC falling; for V_CC rising, the actual threshold is
V_TRIP + V_HYST.
This specification is valid for each 16-byte memory page.
Not production tested. Either guaranteed by design (GBD) or guaranteed by a reliability study (EEPROM lifetime
parameters).
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time storage at
elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40
years at +85°C.
Valid with 32KHz crystal, 12.5pF, ESR ≤ 45kΩ, +25°C.
Total PIO sink and source currents through all PIO pins must be externally limited to less than the absolute
maximum rating of 270mA minus 1.5mA for EEPROM programming and SPI communication. Exceeding the
absolute maximum rating can cause damage.
Assumes the configuration of the system and the part is such that changing GOV<i> (0 ≤ i ≤ 11) between ‘b1 and
‘b0 switches between sourcing no current and sinking the absolute maximum current at the PIO<i> pin. The limit
refers to the switching time between sinking 20% of the DC current and 80% of the DC current. The same is true
for changing between 'b0 and 'b1 causing the part to switch from sinking no current to sourcing the absolute
maximum current at the PIO<i> pin.
Each output pin transitions in 1µs with a pause of 1µs before the next pin transitions.
All PIO are tri-stated at beginning of reset prior to setting to power-on values.
If the part has battery power (normal case) the active pulldown of RSTZ is supported by the battery.
If V_BAT is tied to V_CC (no battery supply) the state of the RSTZ pulldown transistor is not guaranteed when V_CC falls
below V_POR.
Threshold refers to the manual reset function obtained by forcing RSTZ low.
Transient response to a step on V_CC from above V_TRIP down to (V_TRIP - 1mV). Glitches on V_CC that are shorter than
t_DELmin are guaranteed to be suppressed, regardless of their amplitude. Glitches on V_CC that are longer than t_DELmax
are guaranteed not to be suppressed. This parameter is tested at high V_CC and guaranteed by design at low.
If enabled, this test takes place every hour on the hour. The battery voltage is compared to V_BTP during the second
half of the t_BTPW window. The timing is controlled by the RTC.
Extended duration applies to the following cases:
1) Aborted WREN, WRDI, RDSR, and WRSR command.
2) WRITE command aborted before transmitting the first complete data byte after command and address.
3) READ command aborted before reading the first complete data byte after command and address.
4) Read aborted before the end of a byte.
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