DS1642 Datasheet, PDF (4/11 Pages) Dallas Semiconductor – Nonvolatile Timekeeping RAM

RETRIEVING DATA FROM RAM OR CLOCK
DS1642
The DS1642 is in the read mode whenever WE (write enable) is high, and CE (chip enable) is low. The
device architecture allows ripple–through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t_AA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip enable access (t_CEA) or at output enable access time (t_OEA). The state of the
data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before t_AA, the data
lines are driven to an intermediate state until t_AA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (t_OH) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1642 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t_WR prior to the initiation of another read or
write cycle. Data in must be valid t_DS prior to the end of write and remain valid for t_DH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs t_WEZ after WE goes active.
DATA RETENTION MODE
When V_CC is within nominal limits (V_CC > 4.5 volts) the DS1642 can be accessed as described above by
read or write cycles. However, when V_CC is below the power-fail point V_PF (point at which write
protection occurs) the internal clock registers and RAM is blocked from access. This is accomplished
internally by inhibiting access via the CE signal. When V_CC falls below the level of the internal battery
supply, power input is switched from the V_CC pin to the internal battery and clock activity, RAM, and
clock data are maintained from the battery until V_CC is returned to nominal level.
BATTERY LONGEVITY
The DS1642 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the V_CC supply is not present. The capability of this internal power supply
is sufficient to power the DS1642 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of V_CC power. Each DS1642 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When V_CC is first applied at a level greater than
V_PF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1642 will be much longer than 10 years since no lithium battery energy is consumed when V_CC is
present.
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