DS21FT44 Datasheet, PDF (36/110 Pages) Dallas Semiconductor – 4x3 Twelve Channel E1 Framer, 4x4 Sixteen Channel E1 Framer

SYMBOL
POSITION NAME AND DESCRIPTION
DS21FT44/DS21FF44
Sa7S
Sa6S
Sa5S
Sa4S
ODM
AEBE
PF
TCR2.6
TCR2.5
TCR2.4
TCR2.3
TCR2.2
TCR2.1
TCR2.0
Sa7 Bit Select. Set to one to source the Sa7 bit from the
TLINK pin; set to zero to not source the Sa7 bit. See Section
22 for timing details.
Sa6 Bit Select. Set to one to source the Sa6 bit from the
TLINK pin; set to zero to not source the Sa6 bit. See Section
22 for timing details.
Sa5 Bit Select. Set to one to source the Sa5 bit from the
TLINK pin; set to zero to not source the Sa5 bit. See Section
22 for timing details.
Sa4 Bit Select. Set to one to source the Sa4 bit from the
TLINK pin; set to zero to not source the Sa4 bit. See Section
22 for timing details.
Output Data Mode.
0 = pulses at TPOSO and TNEGO are one full TCLKO
period wide
1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period
wide
Automatic E–Bit Enable.
0 = E–bits not automatically set in the transmit direction
1 = E–bits automatically set in the transmit direction
Function of RLOS/LOTC Pin.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB)
FLB
THDB3 TG802 TCRC4
RSM
RHDB3 RG802
(LSB)
RCRC4
SYMBOL
POSITION NAME AND DESCRIPTION
FLB
THDB3
TG802
TCRC4
RSM
RHDB3
CCR1.7
CCR1.6
CCR1.5
CCR1.4
CCR1.3
CCR1.2
Framer Loopback.
0=loopback disabled
1=loopback enabled
Transmit HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
Transmit G.802 Enable. See Section 22 for details.
0=do not force TCHBLK high during bit 1 of timeslot 26
1=force TCHBLK high during bit 1 of timeslot 26
Transmit CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
Receive Signaling Mode Select.
0=CAS signaling mode
1=CCS signaling mode
Receive HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
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