DS21FT40 Datasheet, PDF (31/87 Pages) Dallas Semiconductor – Four x Three 12 Channel E1 Framer

SYMBOLS
POSITION NAME AND DESCRIPTION
DS21FT40
RSRE
THSE
CCR3.3
CCR3.2
Receive Side Signaling Re–Insertion Enable. See Section 9 for
details.
0=do not re–insert signaling bits into the data stream presented
at the RSER pin
1=re–insert the signaling bits into data stream presented at the
RSER pin
Transmit Side Hardware Signaling Insertion Enable.
TBCS
RCLA
CCR3.1
CCR3.0
Not applicable for DS21FT40. Should be cleared to zero.
Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
Receive Carrier Loss (RCL) Alternate Criteria.
0=RCL declared upon 255 consecutive zeros (125 us)
1=RCL declared upon 2048 consecutive zeros (1 ms)
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
(MSB)
RLB
–
–
TCM4
TCM3
TCM2
TCM1
(LSB)
TCM0
SYMBOLS
POSITION NAME AND DESCRIPTION
RLB
–
–
TCM4
TCM3
TCM2
TCM1
TCM0
CCR4.7
CCR4.6
CCR4.5
CCR4.4
CCR4.3
CCR4.2
CCR4.1
CCR4.0
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
Not Assigned. Should be set to zero when written.
Not Assigned. Should be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode
that deter-mines which transmit channel data will appear in the
TDS0M register. See Section 8 for details.
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
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