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DS1632 Datasheet, PDF (3/6 Pages) Dallas Semiconductor – PC Power-Fail and Reset Controller
DS1632
OPERATION – POWER-FAIL, BATTERY BACKUP
The DS1632 provides a switch to direct power from the battery (VBAT) or the incoming supply (VCC),
depending on which is greater. This switch has a voltage drop of less than 0.3 volts. The VCC input is
constantly monitored by a precision comparator for an out-of-tolerance condition. When such a condition
occurs, the power-fail signals are driven to their active state immediately. The reset signals are also driven
active, but this action is delayed by a time determined by the level of the input on the reset duration pin
(RD). If RD is tied to ground then reset signals will become active after 9 ms. If RD is tied to VCC, then
reset signals will become active after 18 ms. Once active, both the reset signals and the power-fail signals
will remain active as long as a (VCC) out-of-tolerance condition persists. If an out-of-tolerance condition
is not long enough to activate the reset signals, then only the power-fail signals would be affected. When
power returns to within nominal limits the power-fail signals will return immediately to the inactive state.
However, the reset signals remain in the active state for a time which is dependent on the state of the RD
pin. If RD is tied to ground, the reset signals will remain active for 95 ms. If RD is tied to VCC, then the
reset signals will remain active for 190 ms after power is within nominal limits. The delay action on the
reset signals allows time for the power supply and microprocessor clock oscillators to stabilize. The
tolerance pin (TOL) selects the point at which power-fail detection occurs. With the tolerance pin
grounded, power-fail detection occurs in the range of 4.75V to 4.5V. If the tolerance pin is connected to
VCC, then power-fail detection occurs in the range of 4.5V to 4.25V. During most power supply
conditions the VCC input will supply power to all functions within the chip and also to the VCCO pin. The
battery pin (VBAT) only supplies power when VCC is less than VBAT. When VCC is below the level of VBAT
only the VCCO and the OSC OUT pin remain powered by VBAT. All other outputs will be driven to ground
when in a logic low state and will be driven to VCC when in a logic high state. This is done to preserve
battery capacity by avoiding battery drain resulting from loads on these outputs. The output ground level
will be maintained for all levels of VCC, even VCC = GND. However, the output VCC level will be
maintained only for VCC > 2.0V. Internal battery power consumption is less than 2 mA while VBAT is
supplying power. The external load on OSC OUT and VCCO must be added to internal consumption to
determine the total load on the battery.
OPERATION - PUSHBUTTON RESET
The DS1632 provides an input pin for direct connection to a pushbutton. The pushbutton reset input
PBRST requires an active low level input. While TTL levels are sufficient to properly activate this input,
it has been primarily designed for contact closure. Internally, this input is debounced and timed such that
RST and RST signals of 95ms or 190 ms minimum are generated. If RD is tied to ground, then a reset
pulse of 95 ms is generated. If RD is tied to VCC then a reset pulse of 190 ms is generated. The delay time
is started as the pushbutton reset input is released from low level.
OPERATION - LOW BATTERY WARNING
The DS1632 provides outputs which warn of a low battery condition. Whenever VCC is within nominal
limits, the VBAT input is continuously monitored. If the VBAT input is out of tolerance, the low battery
outputs are driven to their active states, and will remain in the active state as long as VCC is within
nominal limits or until the battery input is restored to an in limit status. On power-up, if the VBAT input is
out of tolerance, the low battery outputs are not guaranteed active until power-fail is deactivated, but
guaranteed active prior to reset inactive. When VCC is below the VCC fail trip point both LB and LB will
be driven to ground.
For application information, please reference Application Note 64, published separately.
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