DS1744 Datasheet, PDF (2/18 Pages) Dallas Semiconductor – Y2K-Compliant, Nonvolatile Timekeeping RAMs

DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
A0–A14
CE
OE
WE
- Address Input
- Chip Enable
- Output Enable
- Write Enable
V_CC
GND
- Power-Supply Input
- Ground
DQ0–DQ7 - Data Input/Output
N.C.
- No Connection
RST
- Power-On Reset Output (PowerCap module board only)
X1, X2
V_BAT
- Crystal Connection
- Battery Connection
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
DS1744-70
DS1744-70IND
DS1744P-70
DS1744P-70IND
DS1744W-120
DS1744W-120IND
DS1744WP-120
DS1744WP-120IND
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
28 PDIP Module
28 PDIP Module
34 PowerCap*
34 PowerCap*
28 DIP Module
28 DIP Module
34 PowerCap*
34 PowerCap*
*DS9034PCX (PowerCap) required. (Must be ordered separately.)
VOLTAGE
(V)
5
5
5
5
3.3
3.3
3.3
3.3
TOP MARK
DS1744-70
DS1744-70IND
DS1744P-70
DS1744P-70IND
DS1744W-120
DS1744W-120IND
DS1744WP-120
DS1744WP-120IND
DESCRIPTION
The DS1744 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 32k x 8
NV SRAM. User access to all registers within the DS1744 is accomplished with a byte-wide interface as
shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations.
The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock
registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles.
The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by
access to time register data. The DS1744 also contains its own power-fail circuitry that deselects the
device when the V_CC supply is in an out-of-tolerance condition. This feature prevents loss of data from
unpredictable system operation brought on by low V_CC as errant access and update cycles are avoided.
2 of 18