DS1222 Datasheet, PDF (2/4 Pages) Dallas Semiconductor – BankSwitch Chip

OPERATION - BANK SWITCHING
DS1222
Initially, on power-up all four bank select outputs are low and the chip enable output ( CEO ) is held high.
(Note: the power fail input [ PFI ] must be low prior to power-up to assure proper initialization.) Bank
switching is achieved by matching a predefined pattern stored within the DS1222 with a 16-bit sequence
received on four address inputs. Prior to entering the 16-bit pattern, which sets the bank switch, a read
cycle of 1111 on address inputs AW through AZ should be executed to guarantee that pattern entry starts
with bit 0. Each set of address inputs is clocked into the DS1222 when CEI is driven low. All 16 inputs
must be consecutive read cycles. The first eleven cycles must match the exact bit pattern as shown in
Table 1. The last five cycles must match the exact bit pattern as shown for addresses AX, AY, and AZ.
However, address line AW defines the bank number to be enabled as per Table 2.
Switching to a selected bank of memory occurs on the rising edge of CEI when the last set of bits is input
and a match has been established. After bank selection CEO always follows CEI with a maximum
propagation delay of 15 ns. The bank selected is determined by the levels set on Bank Select 1 through
Bank Select 4 as per Table 2. These levels are held constant for all memory cycles until a new memory
bank is selected.
ADDRESS BIT SEQUENCE Table 1
BIT SEQUENCE
ADDRESS
INPUTS
012345678
A_W
101000110
A_X
010111001
A_Y
101000110
A_Z
010111001
BANK SELECT CONTROL Table 2
Bank
A_W Bit Sequence
Selected
11
12
13
14
15
*Banks Off
0
X
X
X
X
Bank 0
1
0
0
0
0
Bank 1
1
0
0
0
1
Bank 2
1
0
0
1
0
Bank 3
1
0
0
1
1
Bank 4
1
0
1
0
0
Bank 5
1
0
1
0
1
Bank 6
1
0
1
1
0
Bank 7
1
0
1
1
1
Bank 8
1
1
0
0
0
Bank 9
1
1
0
0
1
Bank 10
1
1
0
1
0
Bank 11
1
1
0
1
1
Bank 12
1
1
1
0
0
Bank 13
1
1
1
0
1
Bank 14
1
1
1
1
0
Bank 15
1
1
1
1
1
* CEO =V_IH independent of CEI
2 of 4
9 10 11 12 13 14 15
10xxxxx
0100011
1011100
0100011
X See Table 2
BS1
Low
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Outputs
BS2
Low
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
BS3
Low
Low
Low
Low
Low
High
High
High
High
Low
Low
Low
Low
Low
High
High
High
BS4
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
High