DS1851 Datasheet, PDF (17/17 Pages) Dallas Semiconductor – Dual Temperature-Controlled NV Digital-to-Analog Converters

DS1851
NOTES:
1. All voltages are referenced to ground.
2. A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT > 250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t_RMAX + t_SU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
3. After this period, the first clock pulse is generated.
4. The maximum t_HD:DAT has only to be met if the device does not stretch the LOW period (t_LOW) of the
SCL signal.
5. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VI_{H MIN} of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
6. C_B - total capacitance of one bus line in pF, timing referenced to (0.9)(V_CC) and (0.1)(V_CC).
7. EEPROM-write begins after a STOP condition occurs.
8. Measured with SDA = SCL = V_rc = V_CC, and V_rg = GND. The outputs OutV and OutG are left open.
9. Valid at 25°C only.
10. With V_rc = V_CC -1.25 and V_rg = 1.25 + GND.
11. 0.8% is equivalent to 2 LSB.
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