DS21458 Datasheet, PDF (144/270 Pages) Dallas Semiconductor – Quad T1/E1/J1 Transceivers

DS21455/DS21458 Quad T1/E1/J1 Transceivers
Register Name:
Register Description:
Register Address:
H1RC, H2RC
HDLC #1 Receive Control, HDLC #2 Receive Control
31h, 32h
Bit #
7
6
5
Name
RHR RHMS
—
Default
0
0
0
4
3
2
—
HDLCD
—
0
0
0
1
0
—
RSFD
0
0
Bit 0/Receive SS7 Fill In Signal Unit Delete (RSFD).
0 = normal operation. All FISUs are stored in the receive FIFO and reported to the host.
1 = When a consecutive FISU having the same BSN the previous FISU is detected, it is deleted without host
intervention.
Bit 1/Unused, must be set to zero for proper operation.
Bit 2/Unused, must be set to zero for proper operation.
Bit 3/HDLC Disable. (HDLCD) Setting this bit will disable the transmit and receive HDLC function.
0 = transmit and receive HDLC enabled
1 = transmit and receive HDLC disabled
Bit 4/Unused, must be set to zero for proper operation.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Receive HDLC Mapping Select (RHMS).
0 = receive HDLC assigned to channels
1 = receive HDLC assigned to FDL (T1 mode), Sa Bits (E1 mode)
Bit 7/Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Must be cleared and
set again for a subsequent reset.
0 = normal operation
1 = reset receive HDLC controller and flush the receive FIFO
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