DS2404 Datasheet, PDF (13/28 Pages) Dallas Semiconductor – EconoRAM Time Chip

DS2404
The write protect bits, once set, permanently write protects their corresponding counter and alarm
registers, all write protect bits, and certain control register bits as shown in Figure 7. The time/count
registers will continue to count if the oscillator is enabled. If the user wishes to set more than one write
protect bit, the user must set them at the same time. Once a write protect bit is set it cannot be undone,
and the remaining write protect bits, if not set, cannot be set.
The programmable expiration takes place when one or more write protect bits have been set and a
corresponding alarm occurs. If the RO (read only) bit is set, only the read scratchpad and read memory
function commands are available. If the RO bit is a logic “0”, no memory function commands are
available. The ROM functions are always available.
WRITE PROTECT CHART Figure 7
WRITE PROTECT BIT SET:
WPR
WPI
WPC
Data Protected from
Real Time Clock Interval Timer
Cycle Counter
User Modification:
Real Time Alarm Interval Time Alarm Cycle Counter Alarm
WPR
WPR
WPR
WPI
WPI
WPI
WPC
WPC
WPC
RO
RO
RO
OSC *
OSC *
OSC *
STOP/ START **
DSEL
AUTO/ MAN
* Becomes write “1” only, i.e., once written to a logic “1”, may not be written back to a logic “0”.
** Forced to a logic “0”.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In most instances the
DS2404 behaves as a slave. The exception is when the DS2404 generates an interrupt due to a
timekeeping alarm. The discussion of this bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire port of the DS2404 (I/O pin 5) is open drain with an internal circuit
equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves
attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second and requires a pullup resistor
of approximately 5kΩ .
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120 µs, one or more of the devices on the bus may be reset.
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