DS26502_06 Datasheet, PDF (11/125 Pages) Dallas Semiconductor – T1/E1/J1/64KCC BITS Element

DS26502 T1/E1/J1/64KCC BITS Element
3. BLOCK DIAGRAMS
Figure 3-1. Block Diagram
MCLK
MASTER CLOCK
DS26502
JA CLOCK
RTIP
RRING
RLOS
RAIS
TNEGO
TPOSO
TTIP
TRING
THZE
RLIRLXUIXU
TX
LIU
CLOCK
L
JA
R
+ DATA _O
ENABLED
E
- DATA C
AND IN RX
PATH
M
A
O
L
T
E
L
O
JITTER
ATTENUATOR
L
O
P
CAN BE
O
ASSIGNED TO
RECEIVE OR
O
B
A
TRANSMIT PATH _P
OR DISABLED _B
C
A
K
C
K
M
JA
U
ENABLED
M
X
AND IN TX
PATH
U
X
TX PLL
CLOCK
MUX
T1/E1 SSM
FRAMER
64KCC
DECODER
TX CLOCK
+ DATA
- DATA
T1/E1 SSM
FORMATTER
64KCC
CODER
TCLKO
JTAJGTAPGOPROTRT
PARALLEL/SERIAL CPU I/F
HARDWARE CONTROLLER
JTMS JTRST JTCLK JTDI JTDO
BIS1 BIS0
PARALLEL,
SERIAL, OR
HARDWARE
CONTROLLER
RCLK
LOF_CCE
RSER
RS_8K
400HZ
TCLK
PLL_OUT
TSER
TS_8K_4
TSTRST
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