DS1775_02 Datasheet, PDF (10/14 Pages) Dallas Semiconductor – SOT23-5 Digital Thermometer and Thermostat

DATA TRANSFER ON 2–WIRE SERIAL BUS Figure 4
DS1775
Figure 5 details how data transfer is accomplished on the two–wire bus. Depending upon the state of the
R/W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1775 may operate in the following two modes:
1. Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception
of the slave address and direction bit.
2. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1775 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
SLAVE ADDRESS
A control byte is the first byte received following the START condition from the master device. The
control byte consists of a four bit control code; for the DS1775, this is set as 1001 binary for read and
write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). These bits
are set to 000 (A2="0", A1="0", A0="0") for the DS1775R/TRL and vary according to the device's part
number as specified in the "Ordering Information" section. They are used by the master device to select
which of eight devices are to be accessed. The set bits are in effect the three least significant bits of the
slave address. The last bit of the control byte (R/ W ) defines the operation to be performed. When set to a
"1" a read operation is selected, and when set to a "0" a write operation is selected. Following the START
condition, the DS1775 monitors the SDA bus checking the device type identifier being transmitted. Upon
receiving the 1001 code and appropriate device select bits of 000, the DS1775 outputs an acknowledge
signal on the SDA line.
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